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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-22113-3E
ASSP Communication Network
CMOS
LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces
MB86967
s DESCRIPTION
The MB86967 is a highly-integrated, high-performance single-chip Ethernet LAN controller which contains a PC card interface based on the JEIDA4.2 standard, an ISA bus interface that can be connected directly to the ISA bus, a general-purpose bus interface, a Manchester encoder/decoder based on the IEEE802.3 standard, and 10BASE-T transceiver. The LAN controller and buffer manager are software compatible with the MB86965A and MB86964. The buffer manager has functions for arbitration and buffer management of external buffer memory (SRAM) which can be expanded to 32 KB. These functions provide simultaneous access from the host and data link controller and updating of transmit and receive buffer pointers. This permits substantial reduction of software overhead in buffer management. The Manchester encoder/decoder and 10BASE-T transceiver can be easily interfaced with twisted-pair cable just by addition of a pulse transformer and filter. Mode pin setting allows the system interface to switch between the PC card interface, ISA bus interface, and general-purpose bus interface. When in the ISA bus interface mode, two modes can be selected: a jumperless mode allowing software setting of I/O addresses and interrupt signals, and a jumper mode allowing DIPswitch setting.
s FEATURES
System Interface * Allows switching between PC card interface, ISA bus interface, and general-purpose bus interface * Allows byte swapping of word data according to host CPU (in ISA bus mode and general-purpose bus mode)
(Continued)
s PACKAGE
100-pin Plastic LQFP
(FPT-100P-M05)
MB86967
(Continued) * Has functions for high-speed burst DMA transfer and single DMA transfer (slave operation) (in ISA bus mode and general-purpose bus mode) * Provides node ID EEPROM interface (in ISA bus mode) * Allows software setting of I/O addresses and interrupt signals (in jumperless mode of ISA bus mode) * Can be connected to 8-bit and 16-bit standard microprocessor buses (in general-purpose bus mode) * Provides JEIDA protocol interface (in PC card mode) * Has overlapping address window function (in PC card mode) * Has memory control (common memory, attribute memory, I/O addresses) (in PC card mode)
LAN Interface * Contains Manchester encoder/decoder based on IEEE802.3 standard and 10BASE-T transceiver * Has functions for jabber control, link test, and SQE test * Has functions for inversion detection and automatic correction * Contains LED driver for monitoring network status (link test, collision, transmitting and receiving) * Has function for 10BASE-T external loopback (full-duplex) Controller * Software compatible with MB86965A and MB86964 * Has dual-bank transmit buffer and ring receive buffer (expandable to 32 KB) set by program * Contains 64-bit hash table for multicast address filter * Has function for removing receive long packets (1792-byte or more receive packets) * Has two power-down modes; standby mode (continued crystal oscillation) and shut-down mode (stopped crystal oscillation) Others * Aluminum two-layer wiring CMOS technology * 100-pin LQFP package * Power-supply voltage of 5 V 5%
s PIN ASSIGNMENT
(Top view) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (FPT-100P-M05)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
2
MB86967
* PC card mode Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Symbol VDD1 INPACK WAIT PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 IORD GND1 IOWR PD15 PD14 PD7 PD13 PD6 PD12 GND2 PD5 I/O P O O ID ID ID ID ID ID ID ID ID ID ID IU G IU BD BD BD BD BD BD G BD Pin no. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol VDD2 PD11 PD4 PD3 BCS GND3 BWE BOE BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 BA14 BA13 BA12 BA11 GND4 BA10 BA9 BA8 BA7 I/O P BD BD BD O G O O B B B B B B B B O O O O G O O O O Pin no. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Symbol VDD3
MODE0/LEDL
I/O P IU/OD O O O O G O O O O I ISD ISU OD OD G OD -- P I I I -- --
Pin no. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol GNDA2 TPOPB TPOPA TPONA TPONB VDDA2 CE1 CE2 IOIS16 PD10 GND6 PD2 PD9 PD1 PD8 PD0 IREQ REG VDD4 WE OE ROMAD ROMS ROMRD GND7
I/O G O O O O P IU IU O BD G BD BD BD BD BD O IU P IU IU O O O G
BA6 BA5 BA4 BA3 GND5 BA2 BA1 BA0 CLKO CLKI RESET2 RESET1 LEDR LEDT GNDA1 LEDC NC0 VDDA1 TPIP TPIN GNDM NC1 NC2
I: Input ID: Input with pull-down resistor IS: Schmitt input O:Output BD: Input/output with pull-down resistor IU: Input with pull-up resistor B: Input/output OD:Open-drain output
P: Power supply G:Ground
3
MB86967
* ISA bus mode Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Symbol VDD1 DREQ IOCHRDY SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 ALE IOR GND1 IOW SD15 SD14 SD7 SD13 SD6 SD12 GND2 SD5 I/O P O OD ID ID ID ID ID ID ID ID ID ID ID IU G IU BD BD BD BD BD BD G BD Pin no. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol VDD2 SD11 SD4 SD3 BCS GND3 BWE BOE BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 BA14 BA13 BA12 BA11 GND4 BA10 BA9 BA8 BA7 I/O P BD BD BD O G O O B B B B B B B B O O O O G O O O O Pin no. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Symbol VDD3 LEDL BA6 BA5 BA4 BA3 GND5 BA2 BA1 BA0 CLKO CLKI AEN CHRESET EOP LEDT GNDA1 LEDC
IREQ1/IOSEL0
I/O P OD O O O O G O O O O I ISD ISU ID OD G OD IU/O P I I I/OD IU/O IU/O
Pin no. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol GNDA2 TPOPB TPOPA TPONA TPONB VDDA2 SBHE DMACK IOIS16 SD10 GND6 SD2 SD9 SD1 SD8 SD0 IREQ0 ENHB VDD4 ENLB EEPDO EEPDI EEPCS EEPSK GND7
I/O G O O O O P IU IU OD BD G BD BD BD BD BD O O P O IU O O O G
VDDA1 TPIP TPIN
MODE/LEDR IREQ2/IOSEL1 IREQ3/IOSEL2
I: Input ID: Input with pull-down resistor IS: Schmitt input O:Output BD: Input/output with pull-down resistor IU: Input with pull-up resistor B: Input/output OD:Open-drain output
P: Power supply G:Ground
4
MB86967
* General-purpose bus mode Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Symbol VDD1 DREQ READY SA0 SA1 SA2 SA3 MODE1 N.C RDYPOL BHE DMACK EOP N.C IOR GND1 IOW SD15 SD14 SD7 SD13 SD6 SD12 GND2 SD5 I/O P O O ID ID ID ID ID -- ID ID ID ID -- Iu G Iu BD BD BD BD BD BD G BD Pin no. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol VDD2 SD11 SD4 SD3 BCS GND3 BWE BOE BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 BA14 BA13 BA12 BA11 GND4 BA10 BA9 BA8 BA7 I/O P BD BD BD O G O O B B B B B B B B O O O O G O O O O Pin no. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Symbol VDD3 MODE0 BA6 BA5 BA4 BA3 GND5 BA2 BA1 BA0 CLKO CLKI N.C HWRST LEDR N.C GNDA1 N.C N.C VDDA1 TPIP TPIN GNDM N.C N.C I/O P IU O O O O G O O O O I -- ISU OD -- G -- -- P I I G -- -- Pin no. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol GNDA2 TPOPB TPOPA TPONA TPONB VDDA2 ECS N.C N.C SD10 GND6 SD2 SD9 SD1 SD8 SD0 INT LEDT VDD4 LEDL LEDC N.C SB/SW N.C GND7 P: Power supply G:Ground I/O G O O O O P I -- -- BD G BD BD BD BD BD O OD P OD OD -- O -- G
I: Input ID: Input with pull-down resistor IS: Schmitt input O:Output BD: Input/output with pull-down resistor IU: Input with pull-up resistor B: Input/output OD:Open-drain output
5
MB86967
s PIN DESCRIPTION
* System interface pins in PC card mode Pin no. 18 to 23, 25, 27 to 29, 85, 87 to 91 4 to 14 Symbol PD0 to PD15 Pin name PC CARD DATA BUS I/O BD Function PD15 for most significant bit and PD0 for least significant bit. A built-in 150-k pull-down resistor eliminates the need for any resistor on the card.
PA0 to PA10
PC CARD ADDRESS BUS
ID
PA10 for most significant bit and PA0 for least significant bit. PA0 is invalid at word access. A built-in 150-k pull-down resistor eliminates the need for any resistor on the card. CE1 controls even addresses and CE2 controls odd addresses. At power-on or after reset-canceling, these pins must be kept High for 20 ms to initialize the I/O card. This pin is used to control the output of read data from attribute memory space. This pin is used to control a write operation to attribute memory space. This pin must be kept Non-active High at access to common memory. Keeping this pin Low accesses attribute memory by OE/WE. The I/O area is accessed by IORD/IOWE. Attribute memory is allocated only to even addresses. Therefore, for word access, data signals PD0 to PD7 are valid and PD8 to PD15 are invalid. Access to odd addresses is disabled at byte access. When setting IORD/IOWE Low during DMA operation, REG must be kept High to prevent illegal access.
82 83 96 95 93
CE1 CE2 OE WE REG
CARD ENABLE 1,2
IU
OUTPUT ENABLE WRITE ENABLE REGISTER SELECT
IU IU IU
64
RESET1
HARDWARE RESET1 (Active High)
ISU This pin is used to clear the card configuration register (CCR), set the card to an unset state (IC card interface mode), and initialize the pointers and registers in the LAN controller and 10BASE-T transceiver. When power is applied to the card, the system must keep this pin High or high-impedance for 1 ms after the power supply has stabilized. A builtin 150-k pull-down resistor eliminates the need for any resistor on the card. ISD This pin is internally ORed with RESET1 and contains a 50-k pull-down resistor. IU This pin is used to read data from the I/O area. The MB86967 sends no response to IORD until a write operation to the CCR sets the card to the I/O card interface mode. This pin is used to write data to the I/O area. The MB86967 sends no response to IOWR until a write operation to the CCR sets the card to the I/O card interface mode. A Low level is output to this pin to delay the end of an I/O access cycle in progress.
63 15
RESET2 IORD
HARDWARE RESET2 (Active High) I/O READ
17
IOWR
I/O WRITE
IU
3
WAIT
WAIT
O
(Continued)
6
MB86967
(Continued)
Pin no. 2 Symbol INPACK Pin name INPUT RESPONSE I/O O Function When CE,REG, and IORD are 0s and the address on the address bus agrees with the I/O port in the card, a Low level is output to this pin. When I/O addresses are independent, a Low level is always output to this pin when CE,REG, and IORD are 0s. When 16-bit access (word access) to the I/O port is possible, a Low level is output to this pin. When a High level is output to this pin, the system has 8-bit access (byte access). Note: In the IC memory interface mode (no write operation to the CCR) when power is applied and a reset is canceled, this pin serves as a WP+ (write-protect) pin. Under this condition, a High level is output to this pin (write-protect). 1 should be set in the device ID tuple, WPS, in the CIS to perform a write operation to the card. 92 IREQ INTERRUPT REQUEST O A Low level is output to this pin to request software service from the system. For no interrupt request, a High level is output to this pin. An interrupt signal is sent to one of the interrupt request signals on the bus in the system via the socket interface. Note: In IC memory interface mode (no write operation to the CCR) when power is applied and a reset is canceled, this pin serves as a +RDY/BSY pin. Under this condition, a High level (+RDY) is output to this pin. 98 99 97 ROMS ROMRD ROMAD ROM SELECT ROM READ ROM ADDRESS O O O This pin is used for output of EEPROM OR FLASH chip select signals. This pin is used for output of EEPROM OR FLASH read signals. This pin is used when I/O-reading the I/O number. Connection of this pin to the most significant address of EEPROM OR FLASH permits I/O-reading of address space in the upper half of ROM. For a write operation, both the write enable (WE) and I/O write (IOWR) pins must be enabled. If there is no need to set the ID number in the CIS for I/O-reading, this pin should be kept open.
84
IOIS16
16-BIT I/O PORT
O
7
MB86967
* System interface pins in ISA bus mode Pin no. 18 to 23, 25, 27 to 29, 85, 87 to 91 4 to 13 64 15 17 63 65 Symbol SD0 to SD15 Pin name SYSTEM DATA BUS I/O BD Function These pins are used as data buses for data exchange between the host system and the MB86967. They are also used for DMA transfer. In the 8-bit bus mode (bit 5 of DLCR6 = 1), only the 8 lower bits (SD0 to SD7) are used. These pins are used for input of system address signals for selecting LAN controller registers.
SA0 to SA9 CHRESET IOR IOW AEN EOP
SYSTEM ADDRESS BUS CHIP RESET (Active High) I/O READ (Active Low) I/O WRITE (Active Low) ADDRESS ENABLE (Active High) END OF PROCESS (Active High or Active Low) ADDRESS LATCH ENABLE SYSTEM BUS HIGH ENABLE
ID
ISU This pin is used for input of hardware reset signals. IU IU This pin is used for input of I/O read strobe signals. This pin is used for input of I/O write strobe signals.
ISD This pin is used for input of signals indicating that the DMA controller controls the system bus. ID This pin is used for input of signals indicating the end of DMA transfer between the buffer memory and host system. At input of EOP the next BREQ is not output , and the handshaking cycle is terminated. This pin is used for input of signals indicating that the addresses of SA0 to SA9 are determined. This pin is used for controlling byte/word transfer. In the 16-bit data bus mode (bit 5 (SB/SW) of DLCR6 = 0), this pin, together with SA0, controls word transfer and the transfer of upper and lower bytes on the data bus. SB/SW SBHE 0 0 0 0 1 x: don't care 0 0 1 1 x SA0 0 1 0 1 x Function Word transfer Transfer of upper bytes on data bus (SD15 to SD8) Transfer of lower bytes on data bus (SD7 to SD0) Unused Byte transfer (SD7 to SD0)
14 82
ALE SBHE
ID IU
2
DREQ
DMA REQUEST (Active High)
O
This pin is used for output of DMA transfer request signals.
(Continued)
8
MB86967
(Continued)
Pin no. 69 74 75 92 Symbol
IREQ1/IOSEL0 IREQ2/IOSEL1 IREQ3/IOSEL2 IREQ0
Pin name INTERRUPT REQUEST 0 to 3 (Active High) I/O ADDRESS SELECT
I/O
Function
IU/O Jumperless Mode These pins are used for output of IR signals. One of IREQ0 to IREQ3 is selected by configuration data in EEPROM. Jumper Mode These pins are used to select the I/O base addresses to which the LAN controller is allocated. IOSEL2 IOSEL1 IOSEL0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 I/O Base Address 260H to 27FH 280H to 29FH 2A0H to 2BFH 240H to 25FH 340H to 35FH 320H to 33FH 380H to 39FH 300H to 31FH
83
DMACK
DMA ACKNOWLEDGE I/O CHANNEL READY (Active Low, open-drain output) I/O CHANNEL SELECT 16 (Active Low, open-drain output) ENABLE DATA HIGH (Active Low) ENABLE DATA LOW (Active Low) SHIFT CLOCK DATA IN DATA OUT EEPROM CHIP SELECT (Active High)
I
This pin is used for input of DMAC acknowledge signals indicating that the DMAC is ready to transmit and receive data to and from buffer memory.
3
IOCHRDY
OD This pin is used for output of signals indicating READY for handshaking with the host system. OD This pin is used for output of signals indicating that data transfer is made in a 16-bit I/O access cycle.
84
IOCS16
93 95 99 97 96 98
ENHB ENLB EEPSK EEPDI EEPDO EECS
O O O O IU O
This pin is used for output of enable signals for an external upper system data bus transceiver. This pin is used for output of enable signals for an external lower system data bus transceiver. This pin is used for output of EEPROM shift clock pulses. This pin is connected to DATA IN pin of EEPROM. This pin is connected to DATA OUT pin of EEPROM. This pin is used for output of EEPROM chip select signals.
9
MB86967
* System interface pins in general-purpose mode Pin no. 18 to 23, 25, 27 to 29, 85, 87 to 91 4 to 7 Symbol SD0 to SD15 Pin name SYSTEM DATA BUS I/O BD Function These pins are used as a data bus for data exchange between the host system and the MB86967. They are also used for DMA transfer. In the 8-bit bus mode (bit 5 of DLCR6 = 1), only the 8 lower bits (SD0 to SD7) are used. These pins are used for input of system address signals for selecting MB86967 registers, BOOT PROM, and ID PROM. This pin is used for input of Active-Low chip select signals.
SA0 to SA3
SYSTEM ADDRESS BUS ENABLE CHIP SELECT CHIP RESET I/O READ I/O WRITE END OF PROCESS
ID
82 64 15 17 13
ECS HWRST IOR IOW EOP
IU
ISU This pin is used for input of hardware reset signals (Active High). IU IU ID This pin is used for input of I/O read strobe signals (Active Low). This pin is used for input of I/O write strobe signals (Active Low). This pin is used for input of signals indicating the end of DMA transfer between the buffer memory and host system. At EOP input, the next DREQ is not output and the handshaking cycle is terminated. Either Active High or Active Low can be selected. This pin is used for input of Active-Low signals and for connection of DMAC acknowledge signals indicating that the DMAC is read for transmitting and receiving data to and from buffer memory. This pin is used for input of Active-Low signals and for controlling byte/word transfer. In the 16-bit data bus mode (bit 5 (SB/SW)of DLCR6 = 0), this pin, together with SA0, controls word transfer and the transfer of upper and lower bytes on the data bus. SB/SW SBHE 0 0 0 0 1 x: don't care 0 0 1 1 x SA0 0 1 0 1 x Function Word transfer Transfer of upper bytes on data bus (SD15 to SD8) Transfer of lower bytes on data bus (SD7 to SD0) Unused Byte transfer (SD7 to SD0)
12
DMACK
DMA ACKNOWLEDGE
ID
11
BHE
SYSTEM BUS HIGH ENABLE
ID
92 2
INT DREQ
INTERRUPT REQUEST DMA REQUEST (Active High)
O O
This pin is used for output of Active-Low interrupt request signals. This pin is used for input of DMA transfer request signals.
(Continued)
10
MB86967
(Continued)
Pin no. 3 Symbol READY Pin name READY I/O O Function This pin is used for output of signals indicating READY for handshaking with the host system. Either Active High or Active Low can be selected. This pin is used for selecting the polarity of the READY signal. 1: Active High 0: Active Low This pin is used for output of signals indicating the system bus width. The value of bit 5 of the internal register DLCR6 is reversed. Low: 8-bit data bus mode High: 16-bit data bus mode This pin is used for setting to general-purpose bus mode.
10
RDYPOL
READY POLARITY
ID
98
SB/SW
SYSTEM BYTE/WORD CONFIGURATION
O
8
MODE1
MODE1
ID
* Network interface pins in PC card mode, ISA bus mode, and general-purpose bus mode Pin no. 68 (PC card mode) 68 (ISA bus mode) 96 (General-purpose bus mode) 52 (PC card mode) 52 (ISA bus mode) 95 (General-purpose bus mode) Symbol LEDC Pin name COLLISION LED LINK LED I/O Function OD These pins are used for driving the LED indicating the occurrence of collisions (open-drain output). OD These pins are used for driving the LED indicating the status of the link test (opendrain output). These pins are placed in the link-passed state when the link test is enabled. A Low level is output to this pin when the link test is disabled. When in the power-down or shut-down mode, these pins enter the highimpedance state, regardless of the status of the link test. OD These pins are used for driving the LED indicating transmit-on status (open-drain output). OD These pins are used for driving the LED indicating receive-on status (open-drain output). O These pins are used for output of differential transmit signals from the builtin 10BASE-T transceiver. Preconditioning is performed by two output pins and external filters. These pins are used for input of receive signals from the twisted-pair cable.
LEDL
66(PC card mode) 66 (ISA bus mode) 93 (General-purpose bus mode) 65 (PC card mode) 73 (ISA bus mode) 65 (General-purpose bus mode) 77 78 79 80 71 72
LEDT
TRANSMIT LET RECEIVE LET
LEDR
TPOPB TPOPA TPONA TPONB TPIP TPIN
TWISTED PAIR OUTPUT
TWISTED PAIR INPUT
I
11
MB86967
* Buffer memory interface pins in PC card mode, ISA bus mode, and general-purpose bus mode Pin no. 34 to 41 Symbol BD0 to BD7 Pin name BUFFER MEMORY DATA BUS BUFFER MEMORY ADDRESS BUS I/O B Function These pins are used as data buses for data exchange between the SRAM buffer memory and the MB86967. These pins permit addressing of external SRAM buffer memory expandable to 32 Kbytes.
42 to 45, 47 to 50, 53 to 56, 58 to 60 33 32 30
BA0 to BA14
O
BOE BWE BCS
BUFFER OUTPUT ENABLE BUFFER WRITE ENABLE BUFFER RAM CHIP SELECT
O O O
This pin is used for output of Active-Low signals and for enabling buffer memory at a read operation. This pin is used for output of Active-Low signals and for enabling buffer memory at a write operation. This pin is used for output of Active-Low signals and RAM chip select signals.
* Other pins in PC card mode, ISA bus mode, and general-purpose bus mode Pin no. 52 Symbol MODE/LEDL (PC card mode) LEDL (ISA bus mode) MODE (General-purpose bus mode) 73 GNDM (PC card mode) MODE/LEDR (ISA bus mode) GNDM (General-purpose bus mode) 61 62 CLKO CLKI CRYSTAL OSCILLATOR MODE SELECT/ RECEIVE LED Pin name MODE SELECT/ LINK LED I/O Function IU/OD This pin serves as a mode select pin or a pin for driving the LED indicating the status of the link OD test according to the mode used. It is pulled-up internally. IU
G I/OD G
This pin serves as a mode select pin or a pin for driving the LED indicating the receive status according to the mode used. It serves as a GND pin in the PC card mode and general-purpose bus mode.
O I
Connect an external 20-MHz crystal oscillator. Input external clock pulses to CLKI. The wiring between CLKO/CLKI and the crystal oscillator should be as short as possible to prevent crosstalk with other signal lines. These pins are used for power supply to the digital sections.
1, 26, 51, 94 70 81 16, 24, 31, 46, 57, 86, 100 67 76 12
VDD1 to VDD4
DIGITAL VDD
--
VDDA1 VDDA2 GND1 to GND7
ANALOG VDD DIGITAL GROUND
-- --
These pins are used for power supply to the encoder/decoder and 10BASE-T transceiver. These pins are used for grounding the digital sections.
GNDA1 GNDA2
ANALOG GROUND
--
These pins are used for grounding the encoder/ decoder and 10BASE-T transceiver.
MB86967
s SETTING EACH MODE
Pin 73 1 0 0 Pin 52 x 1 0 Pin 8 x x 0 Pin 41 (BD0) External pull-up*1 External pull-down*2 x x Operation Mode ISA bus mode (Jumperless mode) ISA bus mode (Jumper mode) PC card mode*3 General-purpose bus mode
x: don't care *1: To set the jumperless mode, pull up pin 41 (BD0) at about 50 k to 150 k . *2: To set the jumper mode, pull down pin 41 (BD0) at about 50 k to 150 k . *3: The PC card mode has a bug. Please refer to the Page 58 errata sheet in this document.
13
MB86967
s BLOCK DIAGRAM
* PC card mode
PC card interface Internal data bus
Internal address bus
PD0 to 15 PA0 to 10 CE1 CE2 REG OE WE IORD IOWR WAIT IOIS16 INPACK IREQ RESET1 RESET2
Data link controller
TEN TXD TCK RXD
Manchester encoder/ decoder
10BASE-T TX-DATA transceiver RX-DATA COL
TPOPB TPOPA TPONA TPONB TPIP TPIN
Configuration register
Data link control register
Transmit data
RCK LEDT control control LEDC LEDR
Buffer memory port Lan card register
Control
Buffer manager
Receive data
Multicast address register
MODE0 /LEDL
COL XCD
Control
ROMS ROMRD ROMAD
LBC
BD0 to BD7 BA0 to BA14
BWE BOE BCS
CLKO CLKI
20 MHz X'tal
14
MB86967
* ISA bus mode
Internal data bus
Internal address bus
SD0 to 15 SA0 to 9 ALE IOR IOW ECS SBHE IOCHRDY IOCS16 DREQ DMACK EOP AEN CHRESET IREQ0 ENHB ENLB EEPSK EEPDI EEPCS EEPDO IOSEL0/IREQ1 IOSEL1/IREQ2 IOSEL2/IREQ3
System interface
Data link controller
TEN TXD TCK RXD
Manchester encoder/ decoder
10BASE-T TX-DATA transceiver RX-DATA COL
TPOPB TPOPA TPONA TPONB TPIP TPIN LEDT LEDL LEDC MODE /LEDR
Data link control register
Transmit data
RCK
Buffer memory port
Control
control Multicast address register
control
Receive data
Buffer manager
COL XCD
Control
LBC
BD0 to BD7 BA0 to BA14
BWE BOE BCS
CLKO CLKI
20 MHz X'tal
15
MB86967
* General-purpose bus mode
TEN TXD TCK RXD Data link control register Buffer memory port
Control Transmit data
SD0 to 15 SBHE SA0 to 3 IOR IOW ECS READY DREQ DMACK EOP RDYPOL RESET MODE0 MODE1 INT
System interface
Internal data bus
Internal address bus
Data link controller
Manchester encoder/ decoder
10BASE-T TX-DATA transceiver RX-DATA COL
TPOPB TPOPA TPONA TPONB TPIP TPIN LEDT LEDL LEDC LEDR
RCK
control Multicast address register
control
Receive data
Buffer manager
Control
COL XCD LBC
BD0 to BD7 BA0 to BA14
BWE BOE BCS
CLKO CLKI
20 MHz X'tal
16
MB86967
s BLOCK DESCRIPTION
The MB86967 has five functional blocks. The functions of each block in the PC card mode, ISA mode, and general-purpose bus mode is explained below.
1. 10BASE-T Transceiver
The 10BASE-T transceiver pre-distorts transmit packets from the Manchester encoder/decoder to be suitable for use in the 10BASE-T jitter template. Filtering is performed by an external active filter. The transceiver passes the received packets through an internal receive filter and transfers them to the encoder/decoder.
2. Manchester Encoder/Decoder
The Manchester encoder/decoder converts NRZ-formatted transmit packets from the data link controller into Manchester code and transfers them to the 10BASE-T transceiver. The encoder/decoder converters the receive packets from the transceiver from Manchester code to NRZ format and transfers them to the data link controller.
3. Data Link Controller
The data link controller performs the function of the data link layer specified in the IEEE802.3 standard. At transmitting, the controller attaches the preamble and CRC code to transmit data from buffer memory and transmits it as serial data to the Manchester encoder/decoder. In the event of a collision, the controller automatically executes the back-off algorithm for re-transmission. At receiving, the data link controller performs address-matching and error checks for receive packets from the Manchester encoder/decoder, removes the preamble and CRC code from the packets, and converts them to serial data before writing to buffer memory. The data link controller has a multicast address filter to recognize up to 64 groups of multicast addresses.
4. Buffer Manager
The MB86967 needs external SRAM (expandable to 32 Kbytes) for buffering transmit and receive data. Buffer memory is divided into a dual-bank transmit buffer and ring receive buffer where all processing such as arbitration of access from the system and network and updating of buffer pointers is performed automatically by the buffer manager. The transmit buffer has a packet chain function for continuously transmitting the packets of data stored in it using one transmit-start instruction.
5. System Interface
Like the MB86965B and MB86964, the mode pin setting allows the system interface to switch between the general-purpose interface, ISA bus interface enabling direct interface with the ISA bus, and PC card interface based on the JEIDA4.2 standard. When in the ISA bus interface mode, a serial EEPROM can be connected for storing node IDs and two modes can be selected: a jumperless mode allowing software setting of I/O addresses and interrupt signals for the LAN controller, and a jumper mode allowing DIP-switch setting.
17
MB86967
s FUNCTIONAL DESCRIPTION
1. Local Buffer Configurations
The MB86967 is designed to operate with local buffer which holds packets received from the host processor prior to transmission and assembles packets received from the network before they are delivered to the host processor. The buffer is implemented by using a single byte-wide SRAM whose size is selected via DLCR6<1> as 8 kbytes (DLCR6<1> = 0) or 32 kbytes DLCR6<1> = 1). See Buffer Access section for information on how the host accesses the buffer memory.
2. Crystal Oscillator
The clock rate of 10 Mbits/s specified by the international LAN standard, ISO/ANSI/IEEE 8802-3, is derived from an on-chip oscillator that is controlled by a 20 MHz crystal connected across pins 61 and 62 (CLKO and CLKI). Capacitance specified by the crystal manufacturer must be connected as shown in Figure 1 to stabilize the effects of stray capacitance that may vary crystal frequency. The 20 MHz clock also serves as an internal phaselocked loop (PLL) reference for decoder clock recovery. Use a crystal with the following specifications: quartz (AT-cut); 20-MHz; frequency acurracy of 50ppm at 25C and 100ppm at 0C to 70C; parallel resonant with 20 pF-load in fundamental mode.
MB86967
CLKO 20 MHz CLKI
20 pF
20 pF
Figure 1 Crystal Oscillator Connection
3. Byte-Order Control
Byte-order control provided by BYTESWEAP bit, DLCR7<0>, provides compatibility with various higher-level protocols, such as TCP/IP and XNS. These protocols may have a different order for transmission of the bytes within a word. When BYTESWEAP is low, the least-significant byte of the word transmits first, followed by the most-significant. When BYTESWEAP is set high, the byte order reverses. This feature applies only when the system bus operates in 16-bit (word) mode. The byte-order control works by reversing, or not reversing, the bytes of all words as they pass between the buffer memory and the system bus. Thus all data stored in the transmit buffer or retrieved from the receive buffer is affected, including nontransmitted headers. This control bit does not affect the MB86967 registers other than the Buffer Memory Port registers, BMPR8 and BMPR9. When using this feature, ensure the reversal of header information as well as packet data in the software driver code. See Table 1 for examples of using least..most and most..least byte ordering.
18
MB86967
4. Register Access
The MB86967 includes four sets of user-accessible registers, all of which are accessible as bytes or words. Each register set contains eight registers. Direct access is available to two sets of registers in the device's register set at a time, via register addresses 00H through 0FH. The Data Link Control Registers set (DLCR0 - DLCR7) is always accessible via addresses 00H to 07H. Access to one of the remaining three sets is accomplished by programming the register bank select bits, DLCR7<3:2>. This selects the register set accessible via addresses 08H to 0FH. The bank-switched registers are the Node ID set , DLCR7 - DLCR15, (for setting the Ethernet Address and performing TDR diagnostics), the Hash Table set, HT8 - HT15, (for setting up multicast address filtering) and the Buffer Memory Port set, BMPR7 - BMPR15. During operation (excluding initialization or diagnostics), the Buffer Memory Port set should normally be selected.
Table 1 Byte Ordering
Data<15:8> FOR TRANSMIT PACKET LEAST....MOST Transmit Length, high byte Destination Address, 2nd byte Source Address, 2nd byte Length Field, low byte* Data Field, 2nd byte MOST....LEAST Transmit Length, low byte* Destination Addr, 1st byte Source Addr, 1st byte Length Field, high byte Data Field, 1st byte FOR RECEIVE PACKET LEAST....MOST Unused, reserved Receive Length, high byte Destination Address, 2nd byte Source Address, 2nd byte Length Field, low byte* Data Field, 2nd byte MOST....LEAST Receive Packet Status Receive Length, low byte* Destination Addr, 1st byte Source Addr, 1st byte Length Field, high byte Data Field, 1st byte Items shown with an asterisk are in numerically reversed byte order 19 Unused; reserved Receive Length, high byte* Destination Addr, 2nd byte Source Addr, 2nd byte Length Field, low byte Data Field, 2nd byte Receive Packet Status Receive Length, low byte Destination Address, 1st byte Source Address, 1st byte Length Field, high byte* Data Field, 1st byte Transmit Length, high byte* Destination Addr, 2nd byte Source Addr, 2nd byte Length Field, low byte Data Field, 2nd byte Transmit Length, low byte Destination Address, 1st byte Source Address, 1st byte Length Field, high byte* Data Field, 1st byte Data<7:0>
MB86967
5. Buffer Access
The Buffer Memory Port register pair BMPR8 and BMPR9 provide 8- or 16-bit data access to the receive and transmit buffers through on-chip FIFOs. To eliminate the need for complicated directional control, FIFOs are dedicated to each direction of data transfer. Writing to the transmit buffer can be interleaved with reading from the receive buffer, with the MB86967 automatically maintaining buffer memory pointers, thus relieving the host of that task. The Buffer Memory port register pair is at address 08H when DLCR7<3:2> are programmed to `10' to select the Buffer Memory Port register set. When using DMA, the buffer memory port is automatically selected when the DMA Acknowledge input, DMACK, is asserted. The host accesses are byte-wide when the system is configured for byte-wide operation and word-wide when the system interface is configured for word-wide operation. In the latter mode, byte-wide access to the buffer memory port is not supported. Data can transfer from the host memory to the transmit buffer, or from the receive buffer to host memory by using string moves, single-transfer programmed I/O moves, or DMA. Select the method that yields the highest system-level efficiency. A rapid transfer process results in best performance. Slow transfer can result in poor throughput and performance, and cause the receive buffer to overflow and lose packets.
6. DMA Operation (ISA, Generic Mode Only)
The MB86967 supports single-cycle and burst DMA operation for data transfers between the host and the packet buffer. Hand-shaking between the MB86967 and the external DMA controller is accomplished by the DREQ and DMACK signals. The end of process input, when asserted by the system DMA controller during a transfer cycle, terminates DMA activity after completion of the current cycle. If a DMA interrupt (DLCR3<5>) is enabled, the MB86967 generates an interrupt after completion of DMA activity. Usually only one DMA operation will be run at a time, although the MB86967 could run two interleaving operations, one reading and one writing. There is only one DMA EOP bit, and only one DREQ pin and one DMACK pin, so most hosts could not support more than one DMA operation at a time.
6.1 DMA Write (Transmit) ISA, Generic Mode Only
Setting the TX DMA Enable bit, BMPR12<0>, enables DMA transfer of data packets from the host memory to the MB86967 transmit buffer. The DMA burst control bits, BMPR13<1:0>, set the maximum number of data transfer cycles (bytes or words) in a single bus acquisition to be 1, 4, 8, or 12. The MB86967, when ready to accept data from the host, sets the DMA request output, DREQ, and the host responds by asserting DMA acknowledge, DMACK, followed by Write Strobe, WR, and placing data on the data bus. The MB86967 asserts the RDY(RDY) output when ready to complete the current data-transfer cycle. (The assertive states of the RDY(RDY) output and the EOP(EOP) input are independently programmable.) The MB86967 accepts the data byte/word into its bus write FIFO and later moves it into buffer memory. At the close of a transfer cycle, the host negates WR. In burst mode and depending on the value of the DREQ EXTND bit, DLCR4<2>, the MB86967 negates DREQ at the next-to-last or last transfer cycle of the burst. The host DMA then completes the last one or two transfer cycles and negates DACK to terminate the burst. To start another burst, the MB86967 reasserts DREQ. The DMA controller asserts the end of process input, EOP(EOP), concurrent with the last required data-transfer cycle to indicate completion of the entire transfer process. This action sets the DMA EOP status bit, DLCR1<5>, and discontinues further data requests from the MB86967. The MB86967 will also generate an interrupt if the DMA EOP interrupt enable bit, DLCR3<5>, is high. The host can use this interrupt to begin action to close the process. The host should reset the MB86967 DMA logic and clear the interrupt by writing 00H to BMPR12. Note: DMA EOP DLCR1<5> must be cleared to close the transmit DMA process before attempting another , DMA process. This is accomplished by writing 00H to BMPR12. When this is done, the DMA EOP bit will clear automatically, clearing the EOP status and interrupt, (if enabled) so it is not necessary to clear the interrupt separately. 20
MB86967
After finishing the loading of packets into the buffer, the host initiates packet transmission. This is done by loading the number of packets to be transmitted into the Transmit Start Register, BMPR10<6:0>, and asserting the Transmit Start bit, TXST, of the same register, BMPR10<7>.
6.2 DMA Read (Receive) ISA, Generic Mode Only
The MB86967 indicates that it has received packets and stored them in the packet buffer with status bits or interrupts. Before attempting to transfer a packet from the buffer, the host processor should read the RX BUF EMPTY bit, DLCR5<6>. If this bit is 0, there are one or more packets ready for transfer in the receive buffer. After reading each packet, the host will check this bit again to see if there are more. Prior to beginning the transfer of a packet from the receive buffer to host memory via DMA, the host must first read the four-byte receive packet header from the buffer to obtain the packet status and the length of the packet in bytes. Calculating from the packet length the number of DMA cycles needed to read the packet, the host will load that number into the cycle counter of the host DMA controller. Next, RX DMA EN, BMPR12<1>, is set to high to enable DMA read operation to transfer the packet to host memory. The DMA burst control bits, BMPR13<1:0>, set the maximum number of data transfer cycles (bytes or words) in a single bus acquisition to be 1, 4, 8, or 12. When it is ready to begin, the MB86967 asserts its DMA Request output, DREQ. The host responds by asserting DMA Acknowledge, DMACK, followed by the Read Strobe, RD. The MB86967 will assert its RDY(RDY) output when it has placed the byte/word on the data bus and is ready to complete the data transfer cycle. The system memory will accept the data, then the host negates RD. The MB86967 shifts the data down in its bus read FIFO, then moves its internal read pointer to point to the next byte/word in the buffer, moving it into the FIFO. In burst mode and depending on the value of the DREQ EXTND bit, DLCR4<2>, the MB86967 negates DREQ at the next-to-last or last transfer cycle of the burst. The host DMA then completes the last one or two transfer cycles and negates DMACK to terminate the burst. The MB86967 reasserts DREQ to repeat the process if it can transfer more data after the host negates DMACK. The DMA controller asserts the end of process input, EOP(EOP) concurrent with the last byte/word data transfer to indicate completion of the entire process. The MB86967 then stops requesting more DMA cycles. When EOP(EOP) is asserted by the host DMA controller, the DMA EOP bit, DLCR1<5>, will be set high, and an interrupt will also be generated, provided it is enabled by a high in the associated interrupt enable bit, DLCR3<5>. This interrupt can be used by the host to initiate the final actions to close the DMA process. The interrupt is cleared and the DMA is disabled and reset by writing 00H to the DMA Enable Register, BMPR12. Note: Clearing RX DMA EN must be done to close the receive DMA process before attempting another DMA process. This is accomplished by writing 00H to BMPR12. When this is done, the DMA EOP bit will clear automatically, clearing the EOP status and interrupt, so it is not necessary to clear the interrupt separately. After completion of the DMA process, RX DMA EN must be reasserted when the host wants to begin reading another packet from the receive buffer by using DMA.
21
MB86967
7. Buffer Controller
TRANSMIT BUFFERS
ONE OR TWO TRANSMIT BUFFER
RECEIVED PACKET n+3 (LAST PART)
CURRENTLY AVAILABLE FREE BUFFER AREA
RECEIVED PACKET n
RECEIVE BUFFER RING (30 KILOBYTES MAX)
RECEIVED PACKET n+1
RECEIVED PACKET n+2 RECEIVED PACKET n+3 (FIRST PART)
Figure 2 Buffer Memory Organization
7.1 General
The MB86967 uses a dedicated buffer memory, organized as shown in Figure 2, for intermediate storage of packets to be transmitted, and of packets received from the network. The MB86967 can operate with 8 or 32 kilobytes of total buffer memory, including both transmit and receive spaces. Memory partitioning into transmit and receive sections is controlled by the system software. The total size of the transmit buffer space can be up to 16 kilobytes. The buffer memory not used for the transmitter is used for the receiver, and is automatically configured as a ring buffer. Packets are stored head-to-toe in the receive buffer, as they are in the transmit buffer. However, each packet in the receive buffer is aligned on an eight-byte boundary. As packets are being stored in the receive buffer, as the end of the linear addressing space is reached, the chip's receive write pointer automatically wraps around to the top of the receive addressing range to make a seamless ring. The receive read pointer does the same as the packets are read out to the system. By programming the sizes allocated to transmit and receive buffers, an optimum usage of the memory can be selected according to the demands of a particular application. The buffer controller keeps track of buffer memory partitioning and allocation and updates internal address pointers automatically for the tasks of transmit, retransmit, receive, rejection of packets with errors and data transfers to and from the host. The host and its drivers are thus relieved of buffer management functions, making the MB86967 easy to operate and substantially reducing software requirements. Packets with errors are normally automatically rejected by the MB86967 as are packets shorter than the IEEE minimum length packet of 60 bytes, excluding Preamble and CRC. Since these tasks can be done faster in hardware than in software, this not only 22
MB86967
off-loads the host system, but it also speeds up the communication processes, yielding higher throughput. As a result, the MB86967 can typically win benchmark performance tests over competing controllers.
7.2 Arbitration of Buffer Access
The buffer controller automatically prioritizes and services requests for access to memory from the transmitter, receiver and host system. The MB86967's arbitration mechanism, illustrated in Figure 3, interleaves accesses to the buffer memory so that the operation appears to be simultaneous: data can be written to or read from the buffer memory by the host via Buffer Memory Port Register 8 (BMPR8), while data is being read from the buffer by the transmitter and/or written in for storage by the receiver. Each interface, whether host system or network access, appears to be served independently by the controller. Each interface has an associated FIFO to provide time for the buffer interleaving. Thus, packet data is pipelined through the system for highest performance and throughput, and the buffer controller supports all the cases of simultaneous access to the buffer memory as follows: 1. Data from the network is stored in the receive buffer. 2. The host retreives packets from the receive buffer. 3. The host loads packet data into the transmit buffer. 4. The transmitter obtains data for transmission from the transmit buffer. 5. Any combination of the above can occur concurrently.
HOST CPU
READ OR WRITE MB86967
TRANSMIT RECEIVE
BUFFER CONTROLLER
INTERLEAVED DATA DEDICATED BUFFER MEMORY NETWORK
Figure 3 Simultaneous Access to Buffer Memory
7.3 Transmit Buffer
The section of the memory used by the transmitter can be configured by programming the Transmitter Buffer Size control bits, DLCR6<3:2>. Configurations include a single buffer 2 kilobytes long, or a pair of banks, each either 2, 4 or 8 kilobytes long, as illustrated in Figure 4. Within each buffer or bank, one or more packets can be written by the system until the available space is too small for another packet. When a single transmit buffer is used, the system and the transmitter time-share the use of the buffer. When two buffers are used, the system can load packets into one of the buffers while the contents of the other are being transmitted. Using dual buffers and loading multiple packets for 'packet chaining' gives the highest rate of transmission. 23
MB86967
At reset, internal pointers are initialized to point to the beginning of one of the transmit buffers. Each time the host writes data to the buffer via the Buffer Memory Port Register, an internal pointer is advanced to the next memory location within the transmit buffer. Once a data byte/word is written, it cannot be read and the internal pointer cannot be reversed. When the host completes loading the transmit buffer, it writes the number of packets it has loaded into TX PKT CNT, BMPR10<6:0> and sets the transmit start bit, BMPR10<7>. When this occurs, the MB86967 will switch banks and will start transmitting at the earliest opportunity. Another automatically-managed pointer, the transmit read pointer, sequences through the bank being transmitted to read the packet data into the transmitter through its FIFO. If a collision occurs, the packet will be automatically retransmitted after a pseudo-random waiting interval called the backoff interval. If there are multiple packets in the buffer, the MB86967 will continue down the list until all are transmitted. Upon reaching the end of the list or chain of packets, the transmitter will stop, update its status bits and, if enabled, generate an interrupt. The details of this operation are described in the section on packet transmission.
7.4 Transmit Packet Header
As shown in Figure 5, each packet within one transmit bank is separated by a non-transmitted, two-byte header containing an 11-bit value which specifies the length of the associated packet in bytes. The length specification includes only what is stored in the buffer (shown in the figure as `DATA'), which are the Destination ID, Source ID, Length, and Data fields of the packet. It does not include the Preamble and CRC fields which are generated by the MB86967 as it transmits the packet, and therefore are not stored in the buffer.
24
MB86967
BANK0 2KILOBYTES
TRANSMIT SECTION
BANK0 2KILOBYTES
TRANSMIT SECTION
BANK0 4KILOBYTES TRANSMIT SECTION BANK1 4KILOBYTES
6KILOBYTES
RECEIVE SECTION
30KILOBYTES
RECEIVE SECTION RECEIVE SECTION
24KILOBYTES
BANK0 2KILOBYTES BANK1 2KILOBYTES
TRANSMIT SECTION
BANK0 2KILOBYTES BANK1 2KILOBYTES
TRANSMIT SECTION BANK0 8KILOBYTES
4KILOBYTES
RECEIVE SECTION
28KILOBYTES
TRANSMIT SECTION RECEIVE SECTION BANK1 8KILOBYTES
16KILOBYTES
RECEIVE SECTION
Using 8k x 8 SRAM
Using 32k x 8 SRAM
Figure 4 Transmit Buffer Configurations
7.5 Receive Buffer
Once initialized and enabled, the receiver will automatically load any error-free incoming packets which pass the address filter into the receive buffer through an on-chip FIFO. An interrupt can be provided to alert the host processor that a packet is available in the buffer. The host processor can read out received packets as they become available. Continuous reception can continue as long as the receive buffer does not become full. If the host processor reads the receive packets from the buffer promptly, the buffer will not fill up. If overflow does occur, the receiver will stop and an interrupt will be generated to indicate the problem. If this occurs, the buffer should be emptied so that reception can resume. As soon as space becomes available in the receive buffer, the receiver will automatically resume reception. The receive buffer size can vary between a maximum of 30 kilobytes when 2 kilobytes are allocated for the transmit section and a 32 kilobyte SRAM is used, to a minimum of 4 kilobytes if 4 kilobytes are allocated for the transmit section and an 8 kilobyte SRAM is used. The receive section dynamically allocates space for each individual incoming data packet, aligning each at an eight-byte `page' boundary. Each received packet is preceded by a four byte header which provides packet status and the length of that data packet. The data packets are linked or chained by internal pointers which use the length value in the packet header to calculate the starting address of the next packet. This buffer format is shown in Figure 6. Since the MB86967 controls its dedicated 25
MB86967
buffer memory, FIFO size and depth are unimportant in this architecture, and need not be considered in system timing considerations. A status bit in one of the MB86967's internal registers informs the host when one or more packets are resident in the receive buffer and available to be read. The host retrieves these packets from the buffer memory by successive reads of BMPR8. Once a data byte/word is read from the buffer memory, internal pointers are advanced to the next byte/word. As data is thus read by the system, that memory becomes available for reception of new packets. The MB86967 automatically rejects an incoming packet if there is not enough buffer space to fully receive that packet. Therefore, there is no chance for packets already received to be `overrun' by incoming packets.
LENGTH LSB LENGTH MSB DATA 1 LENGTH LSB LENGTH MSB DATA 2 LENGTH LSB LENGTH MSB DATA 3 LENGTH LSB LENGTH MSB DATA 4 PACKET 2 PACKET 1
DATA n
UNUSED BUFFER AREA
Figure 5 Transmit Buffer Detail When DLCR5<5>, the ACPT BAD PKTS bit, is set to a `0' (disabled), detection of a bad incoming packet causes the MB86967 to release the buffer space in which that packet is contained and to reset its internal pointers so as to use that space for the next incoming packet. If this bit is set to a `1', a packet with a CRC or alignment error will be accepted and the appropriate error bits in the status field of its header will be set. The same applies to DLCR5<3>, ACPT SHORT PKTS, which when high allows retention of packets below 60 bytes in length, excluding Preamble and CRC (which is shorter than IEEE 802.3 minimum packet size).
26
MB86967
7.6 Skip Packet
Writing a `1' to BMPR14<2> commands the buffer controller to skip the balance of the current receive packet in memory. The bit can then be read to determine completion of the skip process is complete (within 300 ns). If there is another packet, the bit returns to 0 when the chip is ready to read the next packet.
DATA STATUS RESERVED LENGTH LSB LENGTH MSB DATA STATUS RESERVED LENGTH LSB LENGTH MSB DATA PACKET N + 1
PACKET N
UNUSED BUFFER AREA
STATUS RESERVED LENGTH LSB LENGTH MSB DATA
Figure 6 Receive Buffer Detail
7.7 Receive Packet Header
The receive packet header contains four bytes and is stored in the receive buffer preceding each packet. The receive packet header comprises one byte of packet status, an unused byte and two bytes (11 bits) for packet length. Bits 1 through 4 of the status byte are an image of the same bits in the Receive Status Register, DLCR1, with respect to the packet that follows. Bit 5 is the GOOD PKT bit, which when set to 1 indicates that no errors were detected in the packet. Bits 0, 6 and 7 are unused and are always set to 0. See Table 2. The length stored in bytes 3 and 4 of the header specifies the length of the portion of the packet stored in the buffer. This length specification is in bytes, regardless of whether the system interface is programmed for byte or word mode. During reception, the MB86967 strips the Preamble field and checks and strips the CRC field, so, as is the case for the transmit buffer, those fields of the packet are not stored in the buffer. The length specification thus includes only the Destination ID, Source ID, Length, and Data fields of the incoming packet.
27
MB86967
Table 2 Receive Packet Header Status Indications
Condition GOOD PACKET PACKET WITH ERROR N/A (Bit 7) 0 0 N/A (Bit 6) 0 0 Good PKT (Bit 5) 1 0 RMT 0900H (Bit 4) 0/1 0/1 SHORT PKT ERR (Bit 3) X 0/1 ALIGN ERR (Bit 2) X 0/1
CRC ERR (Bit 1)
N/A (Bit 0) X X
X 0/1
0/1 indicates that the value of the bit will be 0 or 1 depending on the condition of the packet. An `X' indicates that the value should be ignored.
8. Transmitter Circuits
Circuits within the transmitter include a transmitter state machine, a small FIFO for pipelining the packet data, preamble generator, CRC generator, parallel to serial converter, backoff generator, interpacket gap timer and time domain reflectometer (TDR) counter. Additional circuits involved in packet transmission are described in the Transceiver section of this document. The transmitter state machine provides sequencing of events for the transmitter, including idle, preamble, data, CRC, interpacket gap, jam and backoff. It detects various transmit error conditions and sets appropriate bits within the DLCR registers. The pipeline FIFO provides elastic buffering that the buffer controller can load with data to be transmitted. The chip's CRC generator calculates the 32-bit CRC on the destination and source address, the length field and the data field as specified by the ISO/ANSI/IEEE 8802-3 specification for Ethernet. This value is appended to the end of the packet when it is transmitted.
8.1 Media Access Control
The MB86967 transmitter state machine implements the Carrier Sense, Multiple Access with Collision Detection (CSMA/ CD) network media-access protocol. The MB86967 monitors the network for any other node's carrier, and defers transmission (collision avoidance) while other nodes are transmitting, except when DSC, DLCR4<0>, is high. Collision detection handles collisions that may still occur when two nodes separated on the network begin transmitting at nearly the same time. All nodes monitor the network for collisions and, when involved in one, transmit a 32-bit jam signal to reinforce the collision and then terminate transmission. After waiting a pseudorandom backoff interval, generated as described below, the node automatically retries transmission of the packet. Packets on the network must be separated by at least 9.6 microseconds, the `interpacket gap' (IPG) during which the network medium is specified to be idle. The MB86967 transmitter state machine measures this IPG starting from the end of a packet on the network, and does not attempt to transmit until the end of the IPG. If carrier reappears on the network during the first two-thirds of the IPG, the MB86967 resets the timer to re-time the IPG from the end of the new transmission. Such an event can occur during a collision, since data and carrier indications can be corrupted by the superimposition of the two packets. During the last one-third of the IPG, the MB86967 ignores the occurrence of a carrier indication, in accordance with 8802-3, to ensure fairness and equality in access to the network. Thus, if one station begins transmission slightly ahead of another, there is no advantage to the earlier start. Both nodes transmit, a collision occurs, and backoff interval differentials resolve the media-access contention.
8.2 Transmit Packet Processing
To transmit one or more packets, the host system first loads the packet(s), preceded by a two-byte header giving their lengths, into a transmit buffer by writing the data to the Buffer Memory Port Register, BMPR8. Only the destination address, source address, length and data fields of the packets are loaded by the system. After the 28
MB86967
packets are loaded into the transmit buffer, the system turns the transmitter on to initiate transmission. Observing the media access protocol, the MB86967 defers transmitting to carrier from other nodes, minimum interpacket gap intervals and backoff intervals, if any, and then begins to serialize the data. It generates the Preamble field at the beginning, and calculates and appends the CRC field at the end. Figure 7 illustrates the standard packet format. The serialized signal is routed to the transceiver section which encodes the data into the required Manchester code, appends an end-of-packet delimiter. The transmitter transmits the packets in the transmit buffer in the order in which they were loaded. If a collision is detected by the transceiver, the transmitter automatically retransmits the packet until successful or until 16 consecutive attempts have ended in collision. In the latter case, depending on the mode selection made at initialization time, the transmitter continues to try to transmit the same packet starting again with a collision count of zero, skips the current packet and tries to transmit the next packet starting with a collision count of zero, or halts and waits for instruction from the host. In the last case, the host can elect to terminate transmission attempts by setting ENADLC, DLCR6<7> to one, continue to attempt to transmit the same packet (collision counter reset), or skip the current packet and try to transmit the next packet(collision count is zero).
DESTINATION LENGTH ADDRESS SOURCE PREAMBLE ADDRESS 8 6 6 2
DATA 46-1500 LENGTHS SHOWN IN BYTES
CRC 4
Figure 7 Packet Format
8.3 Backoff Generator
A 17-bit pseudo-random number generator clocked at the 10 MHz bit rate provides the collision backoff function. Distances between stations become part of the randomizing function. The number generator is sampled at the time of collision, masking all but the appropriate number of bits specified by the 8802-3 backoff algorithm. This value is then counted down at the slot-time rate (512 bit times) to generate the backoff interval. For a first collision, only one bit is used, giving a backoff of either 51.2 microseconds or 0. For a second consecutive collision, two bits are used, and so forth, up to ten bits. From the tenth to the 16th collisions, 10 bits are used. This generates a pseudo-random backoff interval of from 0 to 52.38 ms, the so-called `binary exponential backoff' for collisions per the 8802-3 standard.
8.4 Transmit Error Processing
The MB86967 provides four transmit error status bits in its Transmit Status Register (DLCR0) for reporting the four possible transmit errors. The errors are: 1) loss of carrier during transmission, which usually indicates a medium fault or a collision, 2) collision, 3) 16 consecutive collisions and 4) jabber error, which occurs if the length of a single transmission substantially exceeds the time required to transmit a maximum length packet conforming to the standard. The latter three can be enabled separately to generate interrupts. A status bit in the Transmit Status Register is set in case a collision terminates transmission. Collision counter DLCR4<7:4>, automatically increments after each collision up to the sixteenth collision, at which time it rolls over to zero. Another status bit indicates that sixteen consecutive attempts to transmit a packet have been made and all have been terminated by collision. The occurrence of 16 collisions may indicate a network problem, such as a disconnected cable or terminator, that produces false collisions. While rare, 16 collisions may normally occur.
29
MB86967
8.5 Time Domain Reflectometry
When a node transmits, a short or open on the network causes a reflected signal to the node receiver, which can sometimes be detected. The reflection causes failure of the carrier sense or detection of a false collision. An open on the network may cause a false collision, whereas a short usually causes loss of carrier sense. Time domain reflectometry (TDR) allows estimates of the distance along the network cable from the node to the fault. The MB86967 is equipped with a special counter to perform the TDR function. The contents of the counter after any transmission can be determined by reading the Time Domain Reflectometry registers, DLCR14 (the leastsignificant byte) and DLCR15 (the most-significant byte). Only the lower 14 bits of the counter are equipped, which is more than is needed for an IEEE or Ethernet LAN. The top two bits, DLCR15<7:6>, are always 0. The TDR counter counts the actual number of bits transmitted for each packet before a collision indication, carrier loss indication or completion of transmission, whichever comes first. A complete transmission with no error indications clears the TDR counter. The elapsed time represents twice the signal delay from node to fault. To perform the TDR fault test, first enable interrupts for TMT OK, by setting DLCR2<7> high. An alternative to using the interrupt is to poll the TMT OK bit, looking for a high level. Set the 16 Collisions Register, BMPR11, to 07H for this test (no halt, skip-failed packet). Clear status bits by writing 0FF86H to the Receive and Transmit Status registers. Next, try to transmit a packet length of 600 or more bits. Up to 16 attempts may be made automatically, if collisions are indicated. Upon completion of the transmission attempts, TMT OK goes high, generating an interrupt if so enabled. When this occurs, read the Transmit Status register and the TDR register.
8.6 Interpreting the Results
If the count is zero, no fault was detected. If the count is greater than zero, but smaller than the packet length, a cable fault may exist. If the count is less than 525, a real collision may have occurred during the test. Real collisions normally occur within the first 65 bytes of the packet, including preamble. Note the error status bits, COL and CR LOST. COL high suggests a cable open, whereas CR LOST suggests a short. Repeat the measurement several times, discarding any anomalous values, and average the rest. A cluster of readings at about the same value is a strong indicator of a valid fault measurement. If such a cluster of readings occurs, multiply the average of the cluster by 39 feet to estimate the distance from the node to the fault. [39 feet = (100 ns x 0.8 x 186,282 miles/second x 5280 feet/mile)/2; this assumes the network is mostly coaxial cable with signal propagation speed of approximately 0.8 x C, the speed of light.]
9. Receiver Circuits
The receiver includes a receive state machine, serial-to-parallel conversion, pipe-line FIFO, preamble recognition, bit and byte-framing, address filtering, CRC and other error checking. Additional circuits involved in packet reception are described in the Transceiver section of this document. The receiver state machine provides sequencing of events for the receiver, including idle, busy, address filtering, and data storage, detects receive error conditions and sets appropriate bits within the DLC registers. A small data FIFO provides elastic buffering for synchronization with the buffer controller timing and buffering of data while the buffer controller is servicing other buffer memory access requests.
9.1 Monitoring the Network
Whenever the data link section is enabled (ENA DLC bit, DLCR6<7>, is set to zero), the MB86967 constantly monitors the network for carrier. Signals that exceed the AC and DC squelch thresholds of the transceiver cause the internal carrier sense line to assert, which in turn causes the receiver to attempt to receive a packet. (The transmitter also uses the carrier sense function to defer to transmissions from other nodes.) The receiver monitors the serial data stream from the transceiver for the end-of-preamble bit pattern, a four-bit pattern of 1011 ending the preamble's pattern of alternating ones and zeros. This pattern also provides byte 30
MB86967
and field synchronization for the receiver; the bit immediately following the end of preamble is the first bit of the first byte of the packet's destination address field. When packet transmission is unflawed, carrier sense remains asserted for the duration of the packet, negating just after the last bit of the CRC field is received, when the transceiver detects the end-of-packet symbol at the end of the packet. Loss of carrier sense at any other time may also result from a collision or other network problems.
9.2 Address Filtering
A receive packet can be filtered by applying selectable criteria to the contents of its Destination Address field, which is the first data-bearing field following immediately after the Preamble. There are several control bits in the MB86967's registers which provide programmablility of the filter criteria. The contents of the Destination Address field can be of three basic types. The first data type which can occur in this 48-bit field is a single node address, the unique, single-node address, globally registered with the IEEE. This data type is indicated by a "0" in the first bit position of the address. The second type is the multicast address, an address for a pre-defined group of nodes. The multicast address is indicated by a "1" in the first bit position of the address. The MB86967 filters multicast addresses using a hash function and a 64-bit hash table. Thirdly, a broadcast address is defined as a special case of the multicast address which addresses all nodes on the local network. This address value consists of all "1"s. The MB86967 provides programmable address filtering logic for each of these address types. Among the address filtering selections possible with the MB86967 are the following examples: 1. All Pass (no filtering) 2. Node address and broadcast packets only 3. Node address xxx.xxx, multicast addresses yyy.yyy and zzz.zzz and broadcast packets only
9.3 Hash Table
The Hash Table provides a way to filter incoming multicast packets so the host processor need not process packets that are not of interest. The principle behind this filtering process is based on the arrangement of a large number of elements of an array, or database, to facilitate searching for elements associated with a given key or datum. The hash function is a mathematical or logical function that maps all elements in a domain onto a smaller domain called the hash table. Assume this hashing function as an example: treat the multicast address as a nonnegative 48-bit integer, divide this number by 64 and take the remainder. This function maps all multicast addresses into a 64-element hash table because the remainder must be an integer between 0 and 63. Applying this hashing function results in taking the least-significant six bits of the multicast address as an integer. In the hash table, for each element, 0 through 63, a single bit is stored to indicate if the address is accepted (1) or rejected (0). If, for example, the node belongs to three multicast groups, only three or fewer of the hash table elements store ones, and the rest store zeroes. The scheme allows the acceptance of any number of addresses, including all of them. However, while this filters out most nonspecific addresses, there may be addresses not of interest used on the network that also fall into the accept elements, so filtering may be imperfect. The actual hashing function used in the MB86967 is to calculate the CRC on the multicast address and to store the most-significant six bits of this calculation in a register . The six bits are used to address the elements of the hash table: the three MSBs are used as the Hash Table register address, and the three LSBs are used as the bit address within a register byte. If the addressed Hash Table element yields a `1' and the packet is a multicast packet (first bit of destination address equals 1), and it passes the error filters, the packet will be accepted. The hash filter criteria are only used on multicast addresses, which all start with a one. Node IDs that start with a zero are not filtered by the hash filter. The broadcast address, a special case of the multicast set wherein all the bits are ones, is accepted anyway unless the Reject All Packets mode is selected. 31
MB86967
The hash filter is used only when the Address Filter mode select bit AF1 is 1 and mode select bit AF0 is 0, selecting the Node ID, Broadcast, Multicast + Hash Table mode. Hash Table registers should only be accessed when the Receiver is disabled, i.e., when ENA DLC is high, to avoid interaction with the Receiver. There are eight bytes of registers in the Hash Table containing 64 one-bit elements, as shown in the Table 7.
9.4 Receive Packet Processing
As a packet arrives from the network, its destination address field is tested for the various address filter criteria selected by the Address Filter Mode bits, DLCR5<1:0>, and the Hash Table. Only if the address meets the filter criteria selected will the packet be accepted for storage in the receive buffer. In addition, the packet must be error-free, unless the chip has been enabled to receive flawed packets for diagnostic purposes. If these conditions are met, the packet reception results in the packet being stored in the buffer, its 4-byte header being updated at the end of reception, the BUF EMPTY status bit, DLCR5<6>, being cleared, the RX PKT status bit, DLCR1<7>, being set high and an interrupt being generated if so enabled. The last four bytes of the packet are the CRC field and are checked for correct CRC. The CRC bytes are not transferred to the Receive Buffer. If the packet has an error and reception of such packets has not been enabled, it will be discarded and pointers will be reset to reuse the same portion of the receive buffer for the next packet to arrive. If a flawed packet is accepted for storage for diagnostic purposes, its error(s) will be reported in the status byte of its header (see Receive Packet Header section).
9.5 Receive Error Processing
Status bits in the receive status register are set to indicate errors associated with packet reception. These errors are: 1) bus read error, which occurs if the host system attempts to read from an empty receive buffer (this need never occur if the RX BUF EMPTY bit is checked), 2) short packet error, 3) alignment error (incomplete byte fragment at end of packet), 4) CRC error and 5) buffer overflow, which occurs if the receive buffer space is insufficient to hold the entire received packet (the receive controller automatically removes such packets from the receive buffer and packets already stored in the buffer are not lost). Each of these receive error conditions may optionally generate an interrupt. None of these errors requires special host processing or intervention, other than optional tallying of the error for network management purposes.
10. 10BASE-T Transceiver
The MB86967's transceiver section provides the electrical interface for RJ45 (10BASE-T) connections to the Ethernet local area network. Its functions include Manchester encoding and decoding of serial data streams to the transmitter and from the receiver, level conversion, collision detection, signal quality error (SQE) and link integrity testing, jabber control, loopback, and automatic correction of polarity reversal on the twisted-pair input. Also provided are outputs for transmit, collision and link test pass LEDs, and compatibility with unshielded twisted-pair cables. Receive threshold can be reduced to allow an extended range between nodes in low-noise environments. Programmable functions are controlled via BMPR13. Transceiver status is presented in BMPR15.
10.1 Data Encoder
The encoder converts the serialized NRZ data from the transmitter to Manchester code, the format used on the network medium. In Manchester code a one is represented as a bit cell (nominally 100-nanoseconds) starting with a low, ending with a high, with a low-to-high transition at the midpoint; Manchester code for a zero is the inverse. The encoder also monitors the state of the internal transmit enable signal from the transmitter section and appends an end-of-packet symbol (illegal Manchester code) to the data stream when that signal is negated at the end of the CRC field of the transmitted packet.
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10.2 Transmitter Circuits
The transceiver's transmitter section receives the encoded data from the Manchester encoder and the twistedpair network via the TPO circuit. Advanced integrated pulse-shaping produces an output signal that is predistorted and prefiltered to meet the 10BASE-T jitter template on the TPON and TPOP pins. During idle periods, the MB86967 transmits link integrity test pulses on the TPO circuit if LINK TEST EN, BMPR13<5>, is asserted.
10.3 Jabber Control
An on-chip watchdog timer prevents the chip from locking into a continuous transmit mode. When a transmission exceeds the maximum time limit (specified for the MB86967 as 20 to 150 msec), the watchdog timer disables the transmit and loopback functions and asserts the JABBER error status bit, DLCR0<3>, generating an interrupt if so enabled. Before the MB86967 can exit the jabber state, the transmit data circuit must remain idle for between 0.25 and 0.75 seconds.
10.4 SQE Test
The transceiver supports the signal quality error (SQE) test function specified in the standard. After every successful transmission on the 10BASE-T network, the MB86967 transceiver section transmits the SQE signal to the controller for 105 bit times over the internal CI circuit. BMPR15<1> reflects the status of this SQE test.
10.5 Receive Input Circuits
Valid received signals from the twisted-pair network connection (the TPI circuit) pass through on-chip filters to the data decoder. An internal intelligent squelch function discriminates noise from link test pulses and valid data streams. The receiver is activated only by valid data streams above the squelch level and with proper timing. If the differential signal at the TPI circuit inputs falls below 75% of the threshold level (unsquelched) for eight bit times (typical), the receiver enters the idle state.
10.6 Data Decoder
The data decoder section performs three functions on the received data: clock recovery, carrier detection, and Manchester data decoding. Carrier detection is indicated to the receiver section by assertion of the internal carrier sense signal, which occurs shortly after the received data signals appear. Carrier sense status can be monitored via DLCR0<6>. Clock recovery and data separation are accomplished by an internal phase-locked loop. The recovered clock is supplied to the receiver together with the recovered NRZ serial data stream.
10.7 Reverse Polarity
The transceiver polarity reverse circuit uses link pulses and end-of-frame data to determine the polarity of the received signal. A reversed polarity condition is detected when eight opposite receive link pulses are detected without receipt of a link pulse of the expected polarity. Reversed polarity is also detected if four frames are received with a reversed start-of-idle. Whenever polarity is reversed, these two counters are reset to zero. If the transceiver enters the link fail state and no valid data or link pulses are received within 96 to 128 milliseconds, polarity resets to the default uninverted condition. If Link Integrity testing is disabled, polarity detection is based only on received data. The transceiver automatically corrects reversed polarity. Polarity reversal is reported via BMPR15<3>.
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MB86967
10.8 Collision Detection
The collision detection function operates on the twisted-pair side of the interface. A collision is defined as the simultaneous presence of valid signals on both the TPI circuit and the TPO circuit. The transceiver reports collisions to the back-end via an internal signal. If the TPI circuit is active while there is activity on the TPO circuit, the TPI data passes to the back-end as received data, disabling normal loopback.
10.9 Loopback
The MB86967 provides the automatic local loopback function specified by the 10BASE-T standard for the twistedpair port. This function is in effect except when the LBC bit, DLCR4<1>, is asserted. Data transmitted by the transmitter is passed through the data encoder, internally looped back within the MB86967 before the TPO drivers to the data decoder and returned to the receiver. This local loopback function is disabled when a data collision occurs, clearing the received data circuit in the transceiver for the data arriving at the twisted-pair inputs. The local loopback is also disabled during the link fail and jabber states. The MB86967 provides additional loopback testing functions controlled by LBC. When the twisted-pair port is selected and LBC is asserted, the loopback is forced regardless of the state of the TPI inputs or link test failure. During loopback, data is routed from the transmit buffer to the transmit section of the data link controller, through the Manchester encoder, back through the Manchester decoder, through the receiver section of the data link controller, and is then stored in the receive buffer. Software can then read and check the received packet that has traveled through the MB86967 transmit and receive sections. Receipt of the loopback data into the receive buffer can be disabled by asserting FILTER SELF RX, BMPR14<0>. The transmitted data is blocked from appearing at the network outputs while the MB86967 is in forced loopback mode (LBC asserted).
10.10 Link Integrity Test
The link integrity test determines the status of the receive side twisted-pair cable. Link integrity testing is enabled when LINK TEST EN, BMPR13<5>, is set low. When enabled, the receiver recognizes the link integrity pulses transmitted in the absence of receive traffic. If no serial data stream or link integrity pulses are detected within 50 to 150 milliseconds, the MB86967 enters a link-fail state and disables the transmit and automatic local loopback functions. The MB86967 ignores any link integrity pulse with an interval less than 2 to 7 milliseconds. The MB86967 remains in the link-fail state until it detects either a serial data packet or two or more link integrity pulses.
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s CONTROL REGISTERS IN LAN CONTROLLER
These control registers are used in all modes (PC card mode, ISA bus mode, and general-purpose bus mode). The I/O address space between the base and 0 to F addresses has 32 control registers in the LAN controller for two address-extended bits (RBS1 and RBS0). The two address-extended bits (RBS1 and RBS0) are at bits 3 and 2 of the control register DLCR7 in the LAN controller (base address +7). Notes:1. At reset, the LAN controller defaults to the 8-bit system interface. However, in the PC card mode, the 8-bit or 16-bit interface is set by bit 5 (IOIS8) of CCR1 at switching from the IC memory interface to the I/O card interface according to the CCR setting condition. 2. The PC card mode does not support DMA.
1. Arrangement of Registers
Register name Transmit status Receive status Transmit interrupt enable Receive interrupt enable Transmit mode Receive mode Control 1 Control 2 Node ID 0 Node ID 1 Node ID 2 Node ID 3 Node ID 4 Node ID 5 TDR0 TDR1 Multicast address 0 Multicast address 1 Multicast address 2 Multicast address 3 Multicast address 4 Multicast address 5 Multicast address 6 Multicast address 7 Buffer memory port Transmit packet count 16 collision DMA enable DMA burst/transceiver mode Receive control/transceiver interrupt Transceiver status/control Symbol DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 DLCR8 DLCR9 DLCR10 DLCR11 DLCR12 DLCR13 DLCR14 DLCR15 MAR8 MAR9 MAR10 MAR11 MAR12 MAR13 MAR14 MAR15 BMPR8 BMPR10 BMPR11 BMPR12 BMPR13 BMPR14 BMPR15 System address SA3/PA3 SA2/PA2 SA1/PA1 SA0/PA0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 1 0 1 Register bank RBS1 RBS0 x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 35
MB86967
2. Explanation of Control Registers in LAN Controller 2.1 Data Link Controller Register
(1) DLCR0: Transmit Status Register DLCR0 indicates the transmit status of the data link controller. The external interrupt INT is asserted by setting the bits of DLCR2 corresponding to the status bits, bit 7 and bit 3 to 0. Bit 7 Read Write Initial Value Bit no. 7 Bit name TMT OK (Transmit O.K) TMT OK BIT CLR 0 Bit 6 Bit 5 Bit 4 Bit 3 JABBER BIT CLR 0 Bit 2 COL BIT CLR 0 Function Indicates transmission in progress This bit is set automatically when transmission of all packets in the transmitter buffer is completed. In the single buffer mode, the next transmit data can be transferred from the host system. In the dual buffer mode, transmission of data from the second bank can be started (Bit 7 (TMST) of the BMR10 is set). The dual buffer mode permits transfer of the next transmit data from the host system to one buffer, while the other buffer is transmitting packets. Not affected This bit is cleared. Indicates network empty (no carrier detected) Indicates network in use (carrier detected) Not affected Indicates packets transmitted by this register not received normally. This bit is cleared automatically at the start of transmission of each packet. Indicates packets transmitted by this register received normally. This bit must not be used in normal operation. Not affected No short packet error. This bit is cleared automatically at the start of transmission of each packet. Indicates network carrier detect disappeared during packet transmission. This bit is usually set in the event of a packet collision or physical damage to the cable. Not affected Bit 1 16 COL BIT CLR 0 Bit 0 BUS WR ERR BIT CLR 0
NET BSY TMT REC SRT RKT -- Undefined -- 0 -- 0
Operation Read
Value 0 1
Write 6 NET BSY (Net Busy) Read Write 5 TMT REC (Transmit Packet Receive) Read
0 1 0 1 -- 0
1
Write 4 SRT PKT (Short Packet) Read
-- 0
1
Write
--
(Continued)
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MB86967
(Continued)
Bit no. 3 Bit name JABBER Operation Read Value 0 1 No jabber Indicates transmission suspension with continuous transmission over specified time detected by internal watchdog timer Not affected This bit is cleared. No collision error Indicates occurrence of packet collision on network during packet transmission. The data link controller performs retransmission automatically until 16 collisions occur. The count of collision can be checked by reading bits 7 to 4 of the collision counter register DLCR4. Not affected This bit is cleared. No 16 collision error Indicates collisions occurred 16 times continuously during packet transmission. The operation after 16 collision errors can be set using bits 2 and 1 of the 16 collision control register BMPR11. Not affected This bit is cleared. No bus write error Indicates LSI failed to assert RDY signal within 2.15 s at writing transmit data from system to transmitter buffer. In other words, transmit data could not be written because the transmitter buffer is full. This bit is never set at transmitting based on the normal operation flow. Not affected This bit is cleared. Function
Write 2 COL (Collision Error) Read
0 1 0 1
Write 1 16COL (16 Collision Error) Read
0 1 0 1
Write 0 BUS WR ERR (Bus Write Error) Read
0 1 0 1
Write
0 1
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MB86967
(2) DLCR1: Receive Status Register DLCR1 indicates the receive status of the data link controller. The external interrupt INT is asserted by setting the bits of DLCR3 corresponding to the status bits, bit 7 to 0. Bit 7 Read Write Initial Value Bit no. 7 Bit name PKT RDY (Packet Ready) PKT RDY BIT CLR 0 Bit 6 BUS RD ERR BIT CLR 0 Operation Read Value 0 1 Bit 5 DMA EOP BIT CLR 0 Bit 4 RMT RST BIT CLR 0 Bit 3 RX SRT PKT BIT CLR 0 Bit 2 Bit 1 Bit 0
ALG ERR CRC ERR OVRFLO BIT CLR 0 Function BIT CLR 0 BIT CLR 0
No received packet is in the receiver buffer. Indicates packets from self office received normally and transferred completely to receiver buffer. In other words, at least one packet of receive data is in the receiver buffer. Not affected This bit is cleared. If there are still received packets in the receiver buffer even after the host system has read one packet of receive data from the receiver buffer, this bit is automatically reset. No bus read error Indicates LSI failed to assert RDY signal within 2.15 s at reading data in receiver buffer from host system. In other words, the host system attempted to read data from the receiver buffer, although the buffer has no data to read. Not affected This bit is cleared. Indicates DMA transfer not yet completed during DMA transfer. This bit is cleared when both the DMA RENA and DMA TENA bits of the BMPR12 are cleared. Indicates DMA transfer completed and EOP signal asserted by external DMA controller Not affected This bit is cleared. This clearing should be done by clearing both the DMA RENA and DMA TENA bits of the BMPR12. * : This bit is invalid in the PC card mode.
Write
0 1
6
BUS RD ERR (Bus Read Error)
Read
0 1
Write 5 DMA EOP Read
0 1 0
1
Write
0 1
(Continued)
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MB86967
(Continued)
Bit no. 4 Bit name RMT RST (Remote Reset) Operation Read Value 0 1 Function The received packet is not a remote reset packet. Indicates value of data length field in received packet is 0900H. This bit is set only when the ENA RMT RST bit of DLCR5 is set and a physical address match occurs; it is not set for the multicast address and broadcast address. It is also not set when the ENA SRT PKT bit of DLCR5 is set. Not affected This bit is cleared. It is also cleared automatically at the start of receiving the next packet. No short packet error Indicates data length (address + data length + data) of received packet not more than minimum data length (60 bytes). This bit is set for not more than 6 bytes when the ENA SRT PKT bit of DLCR5 is set. It is not set when a collision occurs at the self-TXPKT. Not affected This bit is cleared. No alignment error Indicates CRC of received packet incorrect and bit count of received data not multiple of 8 Not affected This bit is cleared. No CRC error Indicates CRC of received packet incorrect. This bit is not set when a collision occurs at the self-TXPKT. Not affected This bit is cleared. No overflow error Indicates that data erased because data length of received packet larger than free capacity of receiver buffer memory. Even when this bit is set, data is received normally when the data length of the next packet is smaller than the free capacity of the receiver buffer memory. This bit is set to indicate that the receiver buffer memory is almost full; transfer data immediately from the buffer to the host system. This bit is not set in the loopback mode. Not affected This bit is cleared.
Write
0 1
3
RX SRT PKT (Short Packet)
Read*
0 1
Write 2 ALG ERR (Alignment Error) Read*
0 1 0 1
Write 1 CRC ERR (CRC Error) Read*
0 1 0 1
Write 0 OVRFLO (Overflow Error) Read*
0 1 0 1
Write
0 1
* : The bit 3 to bit 0 are cleared when the new packet is received.
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MB86967
(3) DLCR2: Transmit Interrupt Enable Register The DLCR2 register enables a transmit interrupt. When the bit corresponding to the status bit of DLCR0 is set to 1, the external interrupt INT is asserted when the status bit is set. Bit 7 Read/Write Initial Value Bit no. 7 6 to 4 3 2 1 0 ENA TMT OK 0 Bit 6 0 0 Operation Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Bit 5 0 0 Value 0 1 Not used ENA JABBER ENA COL ENA 16COL ENA BUS RD ERR -- 0 1 0 1 0 1 0 1 Bit 4 0 0 Bit 3 ENA JABBER 0 Bit 2 ENA COL 0 Function Disables TMT OK interrupt Enables TMT OK interrupt The read value is always 0. Write 0 to these bits at writing. Disables JABBER interrupt Enables JABBER interrupt Disables COL interrupt Enables COL interrupt Disables 16COL interrupt Enables 16COL interrupt Disables BUS RD ERR interrupt Enables BUS RD ERR interrupt Bit 1 ENA 16COL 0 Bit 0 ENA BUS WR ERR 0
Bit name ENA TMT OK
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MB86967
(4) DLCR3: Receive Interrupt Enable Register The DLCR3 register enables a receive interrupt. When the bit corresponding to the status bit of DLCR1 is set to 1, the external interrupt INT is asserted when the status bit is set. Bit 7 Read/Write Initial Value Bit no. 7 6 5 4 3 2 1 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ENA PKT ENA BUS ENA DMA ENA ENA RX ENA ALG ENA ENA RDY RD ERR EOP RMT RST SRT PKT ERR CRC ERR OVRFLO 0 0 Operation Read/Write Read/Write 0 Value 0 1 0 1 0 1 0 1 0 1 Read/Write 0 1 0 1 0 1 0 0 0 Function Disables PKT RDY interrupt Enables TMT OK interrupt Disables BUS RD ERR interrupt Enables BUS RD ERR interrupt Disables DMA EOP interrupt Enables DMA EOP interrupt Disables RMT RST interrupt Enables RMT RST interrupt Disables RX SRT ERR interrupt Enables RX SRT ERR interrupt Disables ALG ERR interrupt Enables ALG ERR interrupt Disables CRC ERR interrupt Enables CRC ERR interrupt Disables OVRFLO interrupt Enables OVRFLO interrupt * : This bit is invalid in the PC card mode. 0 0
Bit name ENA PKT RDY ENA BUS RD ERR
ENA DMA EOP Read/Write ENA RMT RST Read/Write ENA RX SRT ERR ENA ALG ERR Read/Write
ENA CRC ERR Read/Write ENA OVRFLO Read/Write
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MB86967
(5) DLCR4: Transmit Mode Register DLCR4 sets the transmitter operation modes, and displays the count of collision occurrence. Bit 7 Read Write Initial Value Bit no. 7 to 4 Bit name COL3 to COL0 (Collision Count) TST1 (Chip Test 1) COL3 -- 0* Bit 6 COL2 -- 0* Operation Read Bit 5 COL1 -- 0* Value -- Bit 4 COL0 -- 0* Bit 3 TST1 0 0 Bit 2 CNTRL 1 Function Displays count of collision until transmission completed. These bits are cleared at the completion of transmission. This is a chip test bit. Always write 0 to this bit at writing to DLCR4. 1 cannot be written to this bit during normal operation. The DREQ signal is negated in the last cycle of DMA transfer. The DREQ signal is negated two cycles before the last cycle of DMA transfer. Bit 1 LBC 1 Bit 0 DSC 0
3
Read/Write
--
2
CNTRL Read/Write (DREQ Control)
0 1
* : This bit is invalid in the PC card mode.
1
LBC (Loopback Control)
Read/Write
0
Forced to enter loopback mode. The loopback is not canceled even when a collision is detected. Transmit data is not output from the TPOP*/TPON* pin. Enters standard loopback mode specified in 10BASE-T standard. The loopback function works only at data transmission. The transmit data is loopbacked to the receiver by the encoder/ decoder. If the MB86967 is in the link fail and jabber states when a collision is detected, the loopback mode is canceled and signals are accepted from the twisted-pair board. When this bit is set to 1, the MB86967 is enabled for duplex transmission. In this case, data can be transmitted irrespective of the state of the receiver, enabling external loopback operation.
1
0
DSC (Disable Carrier Detec)
Read/Write
--
* : These bits are undefined until the first packet is completely transmitted after power-on.
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MB86967
(6) DLCR5: Receive Mode Register DLCR5 sets the receiver operation mode, and displays the status of the receiver buffer memory. Bit 7 Read Write Initial Value Bit no. 7 Bit name TST2 (Chip Test 2) BUF EMP (Buffer Empty) TST2 0 0 Bit 6 BUF EMP -- 1 Operation Read/Write Value -- Bit 5 ACPT BAD PKT 0 Bit 4 ADD SIZE 0 Bit 3 Bit 2 Bit 1 AM1 0 Bit 0 AM0 1
ENA SRT ENA PKT RMT RST 0 0 Function
This is a chip test bit. Always write 0 to this bit at writing to DLCR5. Writing 1 to this bit is prohibited during normal operation. Indicates valid data remaining in receiver buffer memory Indicates no valid data in receiver buffer memory Not affected If the received packet has short packet, alignment, and CRC errors, it is discarded and is not transferred to the receiver buffer. A packet with short packet, alignment, and CRC errors is transferred to the receiver buffer like a normally-received packet. Compares destination addresses of receive packet and ID addresses of node for match at all 6 bytes (48 bits) Compares destination addresses of received packet and ID addresses of node for match only at upper byte and 5 bytes (40 bits) A packet of more than 60 bytes and less than 2 Kbytes can be received. A packet of more than 6 bytes and less than 2 Kbytes can be received. The value of this bit is ignored when bit 5 (ACPT BAD PKT) is set. The remote reset packet is not detected. Checks whether value of data length field in receive packet is 0900H Selects node ID address match detect mode at packet receiving (Tables 3 and 4)
6
Read Write
0 1 -- 0
5
ACPT BAD PKT Read/Write (Bad Packet Receive)
1
4
ADD SIZE (Address Size)
Read/Write
0 1
3
ENA SRT PKT Read/Write (Enable Short Packet Receive)
0 1
2
ENA RMT RST Read/Write (Enable Remote Reset) Read/Write
0 1 --
1 and 0 AM1, AM0 (Address Match Mode)
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MB86967
Table 3 Receiving Packets from Other Nodes
AM1 DLCR5 Bit 1 0 0 0 1 1 1 1 AM0 DLCR5 Bit 0 0 1 1 0 0 1 1 LBC DLCR4 Bit 1 x 0 1 0 1 0 1 SELF RX BMPR14 Bit 0 x x x x x x x Physical Packet ID Match Discarded Discarded Received Discarded Received Discarded Received Multicast Packet Broadcast Lower ID Address ID Packet Mismatch Filter*2 Match*1 Discarded Discarded Discarded Discarded Discarded Discarded Received Discarded Discarded Received Discarded Received Discarded Received Discarded Discarded Received Discarded Discarded Discarded Received Discarded Discarded Discarded Discarded Discarded Discarded Received
Table 4 Receiving Packets Transmitted from Self Office
AM1 DLCR5 Bit 1 0 0 0 1 1 1 1 1 AM0 DLCR5 Bit 0 0 1 1 0 0 1 1 1 LBC DLCR4 Bit 1 x 0 1 0 1 0 1 1 SELF RX BMPR14 Bit 0 x x x x x x 0 1 Physical Packet ID Match Discarded Received Received Received Received Received Received Discarded Multicast Packet Broadcast Lower ID Address ID Packet Mismatch Filter*2 Match*1 Discarded Discarded Discarded Discarded Discarded Received Received Discarded Discarded Received Discarded Received Discarded Received Received Discarded Discarded Received Discarded Discarded Discarded Received Received Discarded Discarded Discarded Discarded Received Discarded Received Received Discarded
*1: Lower ID Match: Receive the packets because a match occurs at the 24 lower bits of the node ID and bit 0 of the node ID register is 1. *2: Address Filter: Receive the packets because bit 0 of the node ID register is 1 and the CRC value of the node ID register is selected by the multicast address register.
44
MB86967
(7) DLCR6: Control Register 1 DLCR6 sets the MB86966 operation modes. Bit 7 Read/Write Initial Value Bit no. 7 Bit name ENA DLC 1 Bit 6 100NS/ 150NS 0 Operation Value 0 Bit 5 SB/SW 1 Bit 4 BB/BW 1 Bit 3 TX BUF SIZE 1 0 Bit 2 TX BUF SIZE 0 1 Function When 0 is written to this bit, the MB86967 is ready for transmitting and receiving. When this bit is 0, the node ID register and multicast address register cannot be accessed. The data link controller and buffer manager in the MB86967 are initialized and both the transmitter and receiver buffers are also initialized. Sets cycle time of external SRAM to 150 ns Sets cycle time of external SRAM to 100 ns. In this case, use SRAM with an access time of 80 ns or less. Selects width of system data bus SB/SW 0 1 System Data Bus 16 bit 8 bit Bit 1 BUF SIZE 1 1 Bit 0 BUF SIZE 0 0
ENA DLC Read/Write (Enable Data Link Controller)
1
6
100NS/150NS (SRAM Cycle Time Select) SB/SW (System Bus Width Select)
Read/Write
0 1
5
Read/Write
--
* PC Card Mode When 1 is written to bit 5 (IOIS8) of the CCR1, the SB/-SW bit is set to 1, placing the system data bus in the byte transfer mode. When 0 is written, the SB/-SW bit is set to 0, placing the system data bus in the word transfer mode. In the PC card mode, writing to the SB/-SW bit is performed by CCR1. Writing from DLCR6 does not affect bit 5. * General-purpose Bus Mode The reversed value of the SB/SW bit is output to the external pin SB/SW. 4 BB/BW (Buffer Memory Bus Width) Read Write 1 -- -- The width of the buffer memory data bus is fixed to 8 bits. The read value of this bit is always 1. Not affected Sets size of transmitter buffer. TX BUF SIZE 1 0 0 1 1 0 0 1 0 1 Bank Capacity 2 Kbyte 2 Kbyte 4 Kbyte 8 Kbyte Bank Count 1 2 2 2 Buffer Capacity 2 Kbyte 4 Kbyte 8 Kbyte 16 Kbyte
3 and 2 TX BUF SIZE 1 Read/Write TX BUF SIZE 0 (Transmitter Buffer Size)
(Continued)
* : This register is accessible only for the device initialization.
45
MB86967
(Continued)
Bit no. 1 Bit name BUF SIZE 1 Operation Read/Write Value -- Function Sets size of external buffer memory (transmitter buffer size + receiver buffer size) BUF SIZE 1 0 1 0 BUF SIZE 0 Read Write (8) DLCR7: Control Register 2 DLCR7 sets the MB86967 operation modes. Bit 7 Read Write Initial Value Bit no. Bit name IDENT1 1 Bit 6 IDENT0 0 Operation Read Value -- Bit 5 STBY 1 Bit 4 RDYPOL -- x Bit 3 RBS1 0 Bit 2 RBS0 0 Function Reading the initial values of these bits permits checking the type of controller used in software. Read values 10: MB86967 Read values 11: MB86965A Read values 01: MB86964 Read values 00: MB86960A Writing to these bits is invalid. The LAN controller is placed in the standby mode. In the standby mode, the clock stops, reducing current consumption to about 10%. When 1 is prewritten to bit 4 of BMPR14, the MB86967 enters the shutdown mode. In this mode, the crystal oscillator stops, reducing the current consumption to about 1%. In the PC card mode, when the PwrDwn bit of CCR1 is set to 1, this bit is set to 0. Writing from DLCR7 to this bit is prohibited. Operating state (not standby state). In the PC card mode, when the PwrDwn bit of CCR1 is set to 0, this bit is set to 1. Writing from DLCR7 to this bit is prohibited. Return from the shutdown mode by resetting. The value of the external pin RDYPOL can be read. In the PC card mode, the read value is always 1. In the ISA bus mode, the read value of this bit is always 0. Not affected Bit 1 EOP/EOP 0 Bit 0 BYTE SWAP 0 0 -- Buffer Size 8 Kbyte 32 Kbyte
The read value of this bit is fixed at 0. Not affected
7 and 6 IDENT1 IDENT0
5
STBY
Read/Write
0
1
4
RDYPOL
Read
--
Write
--
(Continued)
46
MB86967
(Continued)
Bit no. Bit name Operation Read/Write Value -- Function The MB86967 has three internal register sets. Bank switching by these bits allows the system to access each register set. DLCR0 to DLCR7 can always be accessed irrespective of the conditions of register banks. RBS1 RBS2 Address 00H to 07H Address 08H to 0FH 0 0 1 1 1 EOP/EOP Read/Write 0 1 0 BYTE SWAP Read/Write 0 0 1 0 1 DLCR0 to DLCR7 DLCR0 to DLCR7 DLCR0 to DLCR7 DLCR0 to DLCR7 DLCR8 to DLCR15 MAR8 to MAR15 BMPR8 to BMPR15 Reserved 3 and 2 RBS1 RBS0
Sets DMA end signal (EOP) input pin Active Low Sets DMA end signal (EOP) input pin Active High When the system bus is the 16-bit mode, byte swapping is not performed for access to BMPR8. The bus is an Intel 16-bit bus. When the system bus is the 16-bit mode, byte swapping is performed for access to BMPR8, switching between upper and lower data. The bus is a Motorola 16-bit bus.
* : This bit is invalid in the PCMCIA mode.
1
* : Writing 1 to this bit is prohibited in the PC card mode. Always write 0 to this bit.
(9) DLCR8 to DLCR13: Node ID Registers Bit 7 DLCR8 DLCR9 DLCR10 DLCR11 DLCR12 DLCR13 ID7 ID15 ID23 ID31 ID39 ID47 Bit 6 ID6 ID14 ID22 ID30 ID38 ID46 Bit 5 ID5 ID13 ID21 ID29 ID37 ID45 Bit 4 ID4 ID12 ID20 ID28 ID36 ID44 Bit 3 ID3 ID11 ID19 ID27 ID35 ID43 Bit 2 ID2 ID10 ID18 ID26 ID34 ID42 Bit 1 ID1 ID9 ID17 ID25 ID33 ID41 Bit 0 ID0 ID8 ID16 ID24 ID32 ID40
DLCR8 to DLCR13 store the node ID of the self office. After comparing the destination addresses in the receive packet with the values of the node ID registers, the matching packets are received according to the setting conditions of the Address Match Mode bits of DLCR5. Usually, set bit 0 (ID 0) of DLCR8 to 0 (When bit 0 of the destination address is 1, the received data serve as the multicast address and the packet is received according to the setting conditions of the Address Match Mode bits of DLCR5, irrespective of their values). The initial values of the node ID registers are undefined. Reading and writing are possible only when bit 7 (ENA DLC) of DLCR6 is 1.
47
MB86967
(10) DLCR14 and DLCR15: TDR Registers Bit 7 DLCR14 DLCR15 TDR7 0 Bit 6 TDR6 0 Bit 5 TDR5 TDR13 Bit 4 TDR4 TDR12 Bit 3 TDR3 TDR11 Bit 2 TDR2 TDR10 Bit 1 TDR1 TDR9 Bit 0 TDR0 TDR8
DLCR14 and DLCR15 are 14-bit counters that are reset at the start of transmission to count the transmit bits until a collision occurs or the carrier is dropped. They are read-only registers. The read values of bits 7 and 6 of DLCR15 is always 0.
2.2 Multicast Address Registers
Bit 7 MAR8 MAR9 MAR10 MAR11 MAR12 MAR13 MAR14 MAR15 MID7 MID15 MID23 MID31 MID39 MID47 MID55 MID63 Bit 6 MID6 MID14 MID22 MID30 MID38 MID46 MID54 MID62 Bit 5 MID5 MID13 MID21 MID29 MID37 MID45 MID53 MID61 Bit 4 MID4 MID12 MID20 MID28 MID36 MID44 MID52 MID60 Bit 3 MID3 MID11 MID19 MID27 MID35 MID43 MID51 MID59 Bit 2 MID2 MID10 MID18 MID26 MID34 MID42 MID50 MID58 Bit 1 MID1 MID9 MID17 MID25 MID33 MID41 MID49 MID57 Bit 0 MID0 MID8 MID16 MID24 MID32 MID40 MID48 MID56
The multicast address registers select the multicast address packet to receive when the Address Match Mode bits of DLCR5 are set to 1 and 0, respectively. Multicast addresses are input to a 32-bit CRC circuit and grouped into 64 by the six rightmost bits of the calculated CRC. Packets with multicast addresses of groups in which set the bits corresponding to the multicast address registers are received. The initial values of the multicast address registers are undefined. Reading and writing are possible only when bit 7 (ENA DLC) of DLCR6 is 1.
2.3 Buffer Memory Port Registers
(1) BMPR8: Buffer Memory Port Bit 7 BMPR8 BMP7 BMP15 Bit 6 BMP6 BMP14 Bit 5 BMP5 BMP13 Bit 4 BMP4 BMP12 Bit 3 BMP3 BMP11 Bit 2 BMP2 BMP10 Bit 1 BMP1 BMP9 Bit 0 BMP0 BMP8
BMPR8 is a data port for transferring transmit and receive data between the host system and buffer memory. When the system interface is in the byte mode, BMPR8 serves as an 8-bit I/O port. When the system interface is in the 16-bit bus mode, BMPR8 serves as a 16-bit I/O port. In the 16-bit bus mode, other registers can be accessed in both bytes and words, but this register can be accessed only in words. In the 16-bit bus mode, setting bit 0 (BYTE SWAP) of DLCR7 permits order swapping between MSB and LSB, allowing this register to work with both Intel and Motorola processors.
48
MB86967
(2) BMPR10: Transmit Packet Count Register BMPR10 sets the transmit start bit and transmit packet count. Bit 7 Read Write Initial Value Bit no. 7 Bit name TMST 0 TMST 0 Bit 6 TX PKT CNT 6 x Operation Read Write Value 0 0 1 Not affected Starts transmitting packet. When the transmitter buffer is in the single buffer mode, set this bit after transferring the transmit packet from the host to the transmit buffer. When the transmitter buffer is in the dual buffer mode, set this bit after transferring the transmit packet to the transmitter buffer and completing transmission of the packet to the second bank (after the TMT OK bit of DLCR0 is set). These bits are decremented each time transmission of one packet is completed, and display the count of packets that have not been transmitted yet. They are set to 00H after all packets have been transmitted. The MB86967 can start transmitting more than one packet using one transmit command. Set the TMST bit and write the transmit packet count (the count of packet transferred to buffer memory). Bit 5 TX PKT CNT 5 x Bit 4 TX PKT CNT 4 x Bit 3 TX PKT CNT 3 x Bit 2 TX PKT CNT 2 x Function The read value of this bit is always 0. Bit 1 TX PKT CNT 1 x Bit 0 TX PKT CNT 0 x
6 to 0
TX PKT CNT 6 to 0
Read
--
Write
--
49
MB86967
(3) BMPR11: 16 Collision Control Register BMPR11 controls operation of the data link controller after a 16 collisions occur. Bit 7 Read/Write Initial Value Bit no. 7 to 3 2 to 0 Bit name Not used 16COL CNTL 2 to 0 0 0 Bit 6 0 0 Operation Read Write Read/ Write Value 0 0 -- Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 16COL CNTL 2 0 Function The read values of these bits is always 0. Writing 1 is prohibited. Always write 0 at writing. 16COL CNTL 2 1 1 1 0 0 Operation after 16COLs Occur Similar to ordinary collisions, the transmit packet causing 16COLs is retransmitted automatically (Auto Mode). The next packet is transmitted automatically after skipping the transmit packet causing the 16COLs (Auto Mode). When 16COLs occur, stop the transmitted data link controller temporarily. To resume transmission, write the values listed in the table below to this register. These values are valid only when written. Write them to this register each time transmission stops after 16COLs occur (Manual Mode). Operation when Resuming Transmission in Manual Mode Similar to ordinary collisions, the transmit packet causing 16COLs is retransmitted. The next packet is transmitted after skipping the transmit packet causing the 16COLs. Bit 1 16COL CNTL 1 0 Bit 0 16COL CNTL 0 0
1
1
1
0
1
x
16COL CNTL 2 0 0 1 1 1 0 0 1
50
MB86967
(4) BMPR12: DAM Enable Register The BMPR12 controls DMA transfer between the host system and the MB86967. Bit 7 Read Write Initial Value Bit no. 7 to 4 3 x 0 x Bit 6 x 0 x Bit 5 x 0 x Bit 4 x 0 x Bit 3 LONGPKT RCV DIS 0 Bit 2 0 0 Bit 1 DMA RENA 0 Bit 0 DMA TENA 0
Bit name Not used
Operation Read Write
Value -- 0 0 1
Function The read values of these bits are always undefined. Writing 1 is prohibited. Always write 0 at writing. The receive long packet removal function is enabled. Packets with a length of 1792 bytes or more are not received. The receive long packet removal function is disabled. Packets with a length of up to 2047 bytes cannot be received normally. The read value of this bit is always 0. Writing 1 is prohibited. Always write 0 at writing. DMA read operation is disabled. DMA read operation (reading from receiver buffer) is enabled. The DMA write operation is disabled. The DMA write operation (writing to receiver buffer) is enabled. * : Writing 1 to this bit is prohibited in the PC card mode. Always write 0 to this bit.
LONGPKT RCV Read/Write DIS
2 1
Not used DMA RENA
Read/Write Read/Write
-- 0 (*1) 1 (*2)
0
DMA TENA
Read/Write
0 (*1) 1 (*2)
*1: The DLCR1 DMAEOP bit is cleared if the DMA RENA bit and DMA TENA bit are set to "00". *2: Writing "11" to both DMA RENA bit and DMA TENA bit is prohibited.
51
MB86967
(5) BMPR13: DMA Burst/Transceiver Mode Control Register The BMPR13 sets the DMA transfer cycle count between the host system and MB86967 and the operation modes of the 10BASE-T transceiver. Bit 7 Read Write Initial Value Bit no. 7 Bit name I/O BASE UNLOCK I/O BASE UNLOCK 1 Bit 6 0 0 Operation Read/Write Value 0 1 Bit 5 LINK TEST ENA 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Function The I/O base address is not changed even after an I/O-read operation to address X12H. An I/O-read operation to address X12H increments the values of the I/O base address select signals (IOSEL0 to IOSEL2), causing a change in the I/O base address (This is valid only in the jumperless ISA bus mode). The read value of this bit is always 0. Writing 1 is prohibited. Always write 0 to this bit at writing. The link test on the 10BASE-T transceiver is enabled. The link test on the 10BASE-T transceiver is disabled. The read values of these bits is always 0. Writing 1 is prohibited. Always write 0 to these bits at writing. The DMA transfer cycle count is set by one bus request (These bits are invalid in the PC card mode). BRST1 BRST0 0 0 1 1 0 1 0 1 DAM Transfer Cycle Count (Max.) 1 (single DMA) 4 18 12 Bit 1 DMA BRST 1 0 Bit 0 DMA BRST 0 0
6 5 4 to 2
Not used LINK TEST ENA Not used
Read/Write Read/Write Read/Write Read/Write
-- 0 1 -- --
1 and 0 DMA BRST 1 and 0
52
MB86967
(6) BMPR14: Receiver Control/Transceiver Interrupt Enable/Shutdown Register BMPR14 controls interrupts from the receiver buffer pointer and 10BASE-T transceiver. Bit 7 Read Write Initial Value Bit no. 7 6 5 4 Bit name Not used ENA LKF INT Not used SHUT DWN MODE 0 0 Bit 6 ENA LKF INT 0 Operation Read/Write Read/Write Read/Write Read/Write Value -- 0 1 -- 0 1 3 TST3 (Chip Test Read/Write 3) SKIP RX PKT Read/Write -- Bit 5 0 0 Bit 4 SHUT DWN MODE 0 Bit 3 TST3 0 0 Bit 2 SKIP RX PKT 0 Function The read value of this bit is always 0. Always write 0 to this bit at writing. The link fail interrupt is disabled. The link fail interrupt is enabled. The read value of this bit is always 0. Always write 0 to this bit at writing. When bit 5 (STBY) of DLCR7 is set, the MB86967 enters the standby state (oscillation continues). When bit 5 (STBY) of DLCR7 is set, the MB86967 enters the shutdown state (oscillation stops). This a chip test bit. Always write 0 to this bit at writing to the BMPR14. Writing 1 to this bit during normal operation is prohibited. Skipping the receiver buffer pointer is completed. The receiver buffer pointer is being skipped (updated), indicating the transient state from when 1 is written to this bit until skipping the pointer is completed (about 200 ns). Not affected. The receiver buffer pointer is not skipped. When 1 is written to this bit, the receiver buffer pointer is skipped up to the beginning of the next packet. This bit is cleared automatically when skipping is completed. If the packet to be skipped is the last one in the receiver buffer, the BUF EMP bit of DLCR5 is set after the receiver buffer pointer is skipped. This function works only after reading the receive packet header (4 bytes). And, it is prohibited to write "1" when the remainder of the packet becomes 8-byte. The signal quality error interrupt is disabled. The signal quality error interrupt is enabled. When the Address Match Mode bits AM1 and AM0 are 11, the packet transmitted from the self office is also received. When the Address Match Mode bits AM1 and AM0 are 11, the packet transmitted from the self office is not received. Bit 1 ENA SQE INT 0 Bit 0 ENA FILTER 0
2
0 1
0 1
1 0
ENA SQE INT FILTER SELF RX
Read/Write Read/Write
0 1 0 1
53
MB86967
(7) BMPR15: Transceiver Status Control Register BMPR15 indicates the status of the 10BASE-T transceiver. Bit 7 Read Write Initial Value Bit no. 7 6 Bit name Not used LKF 0 0 Bit 6 LKF BIT CLR x Operation Read/Write Read Write 5 and 4 Not used 3 POL REV Read/Write Read Write 2 1 Not used SQE Read/Write Read Value -- 0 1 0 1 -- 0 1 0 1 -- 0 1 Bit 5 0 0 Bit 4 0 0 Bit 3 POL REV BIT CLR x Bit 2 0 0 Function The read value of this bit is always 0. Writing 1 is prohibited. Always write 0 to this bit at writing. No link fail is detected. A link fail is detected. Not affected This bit is cleared. The read value of this bit is always 0. Writing 1 is prohibited. Always write 0 to this bit at writing. Polarity reversal is not detected. Polarity reversal is detected. Not affected This bit is cleared. The read value of this bit is always 0. Writing 1 is prohibited. Always write 0 to this bit at writing. An SQE error is not detected. An SQE error is detected. * : The read value of this bit is always 0 when bit 0 of DLCR4(DSC: Disable Carrier Detect) is enabled (1). Bit 1 SQE BIT CLR 0 Bit 0 0 0
Write 0 Not used Read/Write
0 1 --
Not affected This bit is cleared. The read value of this bit is always 0. Writing 1 is prohibited. Always write 0 to this bit at writing.
54
MB86967
s EXPLANATION OF ISA BUS MODE
1. Jumperless ISA Mode
In this mode, the LAN controller reads the I/O addresses and interrupt outputs from initialization data in external E2PROM after the hardware reset at power-on, and initializes them. It takes about 50 s until initialization is completed. This eliminates the need for on-board DIP switches for address decode selection. The initialization data can be changed because the E2PROM can be read and written. Utilities for changing initialization data allow an inexperienced user to retrieve contentions between I/O addresses and mount a LAN interface card in any personal computer. Only one byte is used for the initialization data in the E2PROM. Second and later bytes should be used to store node ID. Data (node ID) at the second and later bytes should be read bit-by-bit, converted to parallel data, and then written to the node ID registers (DLCR8 to DLCR15).
1.1 Setting at E2PROM
The initial values should be prewritten to the first byte in the E2PROM as shown in Figure 8; the node ID should be prewritten to the second and later bytes. After a hardware reset, the LAN controller reads the initialization data at the first one byte in E2PROM automatically, and sets it at the BMPR19 internal register. Bit 7 INTSEL1 Bit 6 INTSEL0 Bit 5 Bit 4 Not used Bit 3 Bit 2 IOSEL2 Bit 1 IOSEL1 Bit 0 IOSEL0
Setting I/O Addresses IOMSEL2 IOMSEL1 IOMSEL0 0 0 Setting Interrupt Channels INTSEL1 0 0 1 1 INTSEL0 0 1 0 1 Interrupt Channel (Pin) IRQ0 IRQ1 IRQ2 IRQ3 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 I/O Base Address 260H to 27FH 280H to 29FH 2A0H to 2BFH 240H to 25FH 340H to 35FH 320H to 33FH 380H to 39FH 300H to 31FH
Figure 8 Configuration of Bits at First One Byte in E2PROM
55
MB86967
1.2 Setting I/O Base Addresses
After completing jumperless initialization, read 8 bytes (DLCR0 to DLCR7) of the registers in the LAN controller using the system software and check that the initial values in these registers have been read correctly. If they are not read correctly, the I/O addresses are assumed to overlap other I/O addresses, and must be changed. To make a change, read BMPR18 (the read value is meaningless). Each time BMPR18 is read, the values of IOSEL2 to IOSEL0 are incremented from 000 to 111 and the updated values become valid in BMPR19. When the I/O addresses are updated until the values of DLCR0 to DLCR7 can be read properly, the LAN controller is located at the correct I/O addresses. After the I/O addresses have been defined, to prevent them being updated in error when BMPR18 is read, clear bit 7 (I/O BASE UNLOCK) of BMPR13. When the I/O address values found by the above operation are prewritten to E2PROM, the above operation is not needed at the next system startup, which reduces the system startup overhead. Consequently, the above retrieval of I/O addresses is required only when the LAN interface board is first installed in a personal computer.
1.3 Setting Interrupt Signals
The LAN controller has four interrupt output pins. The interrupt output pin from which interrupt signals should be output can be specified by initialization data in E2PROM. If contention occurs between the interrupt signals and other I/O devices, the address decoder cannot be updated like the I/O addresses. Write another address decode value to E2PROM and then restart the system. Repeat the above process until interrupt signals are allocated to the correct address area.
1.4 Restarting System
To restart the system, perform a hardware reset or a write operation to the reset registers RESET0 to RESET7 (any data can be written to any of RESET0 to RESET7). The write operation provides the same condition as the hardware reset except that BMPR16 and BMPR17 are not initialized. Initialization takes about 50 s after canceling a hardware reset, or completing a write operation at the reset registers.
2. Jumper + E2PROM ISA Mode
This mode is the jumperless ISA mode without automatic initialization function. The I/O addresses are set by external pins. The interrupt output pin is fixed at IRQ0. The E2PROM interface functions only to store node ID. Read and write operations from and to E2PROM are performed by the system software. After converting read serial data to parallel data, write the data to the node ID registers (DLCR8 to DLCR15).
3. Performance Comparison between Jumperless ISA Mode and Jumper + E2PROM ISA Mode
Jumperless ISA Mode Automatic initialization E2PROM interface Interrupt output selection (Required) Jumper + E2PROM ISA Mode x (Option) x
56
MB86967
4. Register Arrangement
Registers accessible only in the ISA mode are listed below. Register Name E PROM control E PROM data I/O base address Jumperless setting Reserved Reserved Reserved Reserved Reset 0 Reset 1 Reset 2 Reset 3 Reset 4 Reset 5 Reset 6 Reset 7
2 2
Symbol BMPR16 BMPR17 BMPR18 BMPR19 -- -- -- -- RES0 RES1 RES2 RES3 RES4 RES5 RES6 RES7
System Address SA4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SA3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SA2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SA1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SA0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Register Bank RBS1 x x x x x x x x x x x x x x x x RBS0 x x x x x x x x x x x x x x x x
5. BMPR16: E2PROM Control Register
BMPR16 controls external E2PROM. Bit 7 Read Write Initial Value Bit no. 7 6 Bit name Not used ESK x 0 x Bit 6 x ESK 0 Operation Read Write Read Write 5 ECS Read Write Value -- 0 -- -- -- -- Bit 5 x ECS 0 Bit 4 x 0 x Bit 3 x 0 x Bit 2 x 0 x Function The read value of this bit is undefined. Always write 0 to this bit at writing. The read value of this bit is undefined. Shift clocks to E2PROM are generated by repeatedly writing 1 or 0 to this bit. The read value of this bit is undefined. When 1 is written to this bit, the E2PROM chip select signal is asserted. When 0 is written to this bit, the E2PROM chip select signal is negated. The read values of these bits are undefined. Always write 0s to these bits at writing. 57 Bit 1 x 0 x Bit 0 x 0 x
4 to 0
Not used
Read Write
-- 0
MB86967
6. BMPR17: E2PROM Data Register
BMPR17 is an external E2PROM data port. Bit 7 Read Write Initial Value Bit no. 7 6 to 0 Bit name EDIO Not used EDIO 0 Bit 6 x 0 x Operation Read Write Read Write Value -- -- -- 0 Bit 5 x 0 x Bit 4 x 0 x Bit 3 x 0 x Bit 2 x 0 x Function Port for reading output data from E2PROM Port for writing input data to E2PROM The read values of these bits are undefined. Always write 0s to these bits at writing. Bit 1 x 0 x Bit 0 x 0 x
7. BMPR18: I/O Base Address Register
BMPR18 updates and displays the I/O base addresses (valid only in jumperless mode). Bit 7 Read Write Initial Value Bit no. 7 to 0 Bit name IOBA7 to IOBA0 IOBA7 -- 0 Bit 6 IOBA6 -- 0 Operation Read Bit 5 IOBA5 -- 0 Value -- Bit 4 IOBA4 -- 0 Bit 3 IOBA3 -- 0 Bit 2 IOBA2 -- 0 Function Each time this register is read, the I/O base address select signals (IOSEL2 to IOSEL0) are incremented to update the I/O base addresses. The updated values can be read from bits 2 to 0 of BMPR19. The read values of this register have no meaning. Bit 1 IOBA1 -- 0 Bit 0 IOBA0 -- 0
58
MB86967
8. BMPR19: Jumperless Setting Register
BMPR19 displays the initialization value in the jumperless mode (valid only in jumperless mode). Bit 7 Read Write Initial Value Bit no. 7 to 6 Bit name INTSEL1 INTSEL0 INTSEL1 -- 0 Bit 6 INTSEL1 -- 0 Operation Read Value -- INTSEL1 0 0 1 1 5 to 3 2 to 0 Not used IOSEL2 IOSEL1 IOSEL0 Read Read -- -- INTSEL0 0 1 0 1 Bit 5 x -- 0 Bit 4 x -- 0 Bit 3 x -- 0 Bit 2 IOSEL2 -- 0 Function Display the interrupt channels. Interrupt Channel (Pin) IRQ0 IRQ1 IRQ2 IRQ3 Bit 1 IOSEL1 -- 0 Bit 0 IOSEL0 -- 0
The read values of these bits are undefined. Display the boot ROM addresses. IOSEL2 IOSEL1 IOSEL0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 I/O Base Address 260H to 27FH 280H to 29FH 2A0H to 2BFH 240H to 25FH 340H to 35FH 320H to 33FH 380H to 39FH 300H to 31FH
9. RES0 to RES7: Reset Registers
These 8-byte reset registers are valid only in the ISA bus mode. Writing to these registers (any data can be written to any of RES0 to RES7) allows initialization of the buffer manager, data link controller, Manchester encoder/decoder, and 10BASE-T transceiver. This writing also allows the internal registers to be initialized by a reset, but prohibits initialization of BMPR18 and BMPR19.
59
MB86967
s EXPLANATION OF PC CARD MODE
1. E2PROM/FLASH Interface
Card slot * PA0 to PA10 or more
OE WE Data bus (PD0 to PD7) Data bus (PD8 to PD15)
Address 0 to 10 or more*1
WE
Data 0 to 7
PA0 to PA10
OE WE
PD0 to PD7
PD8 to PD15
CE OE Most significant address*2
E2PROM or FLASH ROM
ROMS ROMRD ROMAD
PC card interface * CCR * LAN card control register * Others
IORD IOWR
* CIS (including ID number) * ID number (I/O space)*2 MB86967
Figure 9 Example of E2PROM/FLASH Interface *1: Changed depending on size of E2PROM or flash ROM [Example] PA0 to PA16 for 128-KB flash ROM *2: To I/O-read the ID number, connect the ROMAD pin to the most significant bit of ROM. If I/O-read is not required, leave the ROMAD pin open to set the ID number in the CIS.
60
MB86967
2. Use of E2PROM and Flash ROM 2.1 Setting ID Number in CIS
ROM Size 128-Kbyte flash ROM 2-Kbyte E2PROM CIS Space 2 Kbytes 2 Kbytes Common Memory Space 126 Kbytes -- CCR Location 7F0H to 7F6H 7F0H to 7F6H Address Pin from System to ROM A0 to A16 A0 to A10 Address Pin from System to MB86966 A0 to A10
[Example of 2-Kbyte E2PEOM]
Index 31 3E0H Index 30 7F6H CCR (R/W) 7F0H CIS (R) 000H Attribute memory space I/O address space 3C0H
Index 3 060H Index 2 040H Index 1 020H
[Example of 128-Kbyte Flash ROM]
1FFFFH Index 31 Common memory (R/W) 800H 7F6H CCR (R/W) 7F0H CIS (R) 000H Attribute memory space I/O address space Common memory space Index 30 3C0H Index 29 3A0H 3E0H
Index 3 060H Index 2 040H Index 1 020H
61
MB86967
2.2 I/O-reading ID Number
ROM Size 128-Kbyte flash ROM 4-Kbyte E2PROM CIS Space Common Memory Space I/O Space CCR Location Address Pin from System to ROM A0 to A10 Address Pin from System to MB86966 A0 to A10 Address Pin from MB86966 to ROM Connect ROMAD pin to A16. Connect ROMAD pin to A11.
2 Kbytes 62 Kbytes 62 Kbytes 7F0H to 7F6H
2 Kbytes
--
2 Kbytes
7F0H to 7F6H
A0 to A10
A0 to A10
[Example of 4-Kbyte E2PEOM]
1FFFFH
ID number (Read only)
Common memory space
Index 31 3E0H Index 30 3C0H
800H 7F6H CCR (R/W) 7F0H CIS (R) 000H Attribute memory space I/O address space
Index 3 060H Index 2 040H Index 1 020H
[Example of 128-Kbyte Flash ROM]
1FFFFH I/O address space I/O address space
Index 31 Index 30
3E0H 3C0H
Index 29 3A0H
ID number (Read only) FFFFH Common memory (R/W) CCR (R/W) 7F0H CIS (R) 000H
800H 7F6H
Common memory space
Index 3 060H Index 2 040H
Attribute memory space
Index 1 020H
62
MB86967
3. Address Space
The configuration of the LAN PC card in the MB86967 (in PC card mode) has up to three address spaces (for common memory, I/O memory, and attribute memory). Table 5 gives the common memory space, I/O memory space, and attribute memory space of the MB86967.
Table 5 Memory Map for PC Card
Common Memory Space*1 (E2PROM or FLASH) I/O Memory Space * Control registers in LAN controller (Core of LAN controller) * LAN card control register (PC card interface) * ID number (E2PROM or FLASH)*2 Attribute Memory Space * Card attribute data register (CIS) (E2PROM or FLASH) * LAN card configuration register (CCR) (PC card interface)
Note: Parts in parentheses are the blocks where each item is located. *1: Common memory space cannot allocated if the E2PROM or flash ROM to be selected is less than 2 Kbytes. *2: Connecting P97 (ROMAD) to the most significant address bit of ROM allows I/O-reading of the ID number. To write to this space, both the IOWR and WE pins must be enabled.
63
MB86967
4. Common Memory Space
Common memory space can be used if the capacity of E2PROM or flash ROM to be selected is large. The address space is located higher than the CIS (card attribute data register) of attribute memory space (See examples of E2PROM and flash ROM in 2). Only even addresses are used in the CIS, but both common memory space even and odd addresses can be used in common memory space. Only byte access (8 bits) is available. Writing to common memory space is possible. Efficient writing is performed by data-polling the selected E2PROM or flash ROM. However, in this case, the PwrDwn bit of CCR1 must be not set for the power-down state without ending writing. Batch erase should not be selected for flash ROM. When erasing common memory in blocks, take care not to erase attribute memory space. (1) Read from Common Memory Mode Byte access (8 bits) Word access (16 bits) High byte only REG 1 1 1 CE2 1 0 0 CE1 0 0 1 OE 0 0 0 WE 1 1 1 PA0 0 1 x x PD8 to PD15 Invalid Invalid Invalid Invalid PD0 to PD7 Even byte Odd byte Invalid Invalid ROMS L L H H ROMRD ROMAD L L H H L L L L
(2) Write to Common Memory Mode Byte access (8 bits) Word access (16 bits) High byte only REG 1 1 1 CE2 1 0 0 CE1 0 0 1 OE 0 0 0 WE 1 1 1 PA0 0 1 x x PD8 to PD15 Don't care PD0 to PD7 Odd byte ROMS L L H H ROMRD ROMAD H H H H L L L L
Don't care Even byte
Don't care Don't care Don't care Don't care
64
MB86967
5. Attribute Memory Space
Attribute memory space has the card attribute data register (CIS) and card configuration register (CCR). It can be accessed in 8 bits from even addresses; odd addresses are invalid. The MB86967 can have access to both 8-bit and 16-bit data. When attribute memory space is accessed in the 16-bit mode, only the data signals D0 to D7 are valid, and D8 to D15 are invalid. CIS is located at 000H to 7EEH, starting with address 0. CCR has four registers, located at 7F0H, 7F2H, 7F4H, and 7F6H. Address 7F0H 7F2H 7F4H 7F6H [Reference] CIS: In E2PROM or flash ROM CCR: In MB86967 (1) Read from CIS Mode Byte access (8 bits) Word access (16 bits) REG CE2 CE1 0 0 1 0 0 0 OE IORD WE PA0 0 0 1 1 1 1 0 1 x PD8 to PD15 Invalid Invalid Invalid PD0 to PD7 Even byte Invalid Even byte ROMS ROMRD ROMAD L H L L H L L L L Symbol CCR0 CCR1 CCR2 CCR3 Register Card configuration option register Card configuration status register Pin replacement register Socket/copy register
(2) Write to CIS Mode Byte access (8 bits) Word access (16 bits) REG CE2 CE1 0 0 1 0 0 0 OE IOWR WE PA0 1 1 1 1 0 0 0 1 x PD8 to PD15 PD0 to PD7 ROMS ROMRD ROMAD L H L H H H L L L
Don't care Even byte Don't care Don't care Don't care Even byte
(3) Read from CCR Mode Address REG CE2 CE1 OE IORD WE PA0 0 1 0 0 0 0 1 1 x PD8 to PD15 Invalid PD0 to PD7 Even byte Even byte ROMS ROMRD ROMAD H H H H H H L L L
Byte access (8 bits) Word access (16 bits)
7F0H to 7F6H
0
1
0
0
1
1
Invalid Invalid Invalid
65
MB86967
(4) Write to CCR Mode Address REG CE2 CE1 OE IOWR WE PA0 0 7F0H to 7F6H 0 1 0 1 1 0 1 0 0 0 1 1 0 x PD8 to PD15 Don't care Don't care Don't care PD0 to PD7 Even byte Don't care Even byte ROMS ROMRD ROMAD H H H H H H L L L
Byte access (8 bits) Word access (16 bits)
6. LAN Card Configuration Register
(1) CCR0: Card Configuration Option Register (00007F0H) The card configuration option register (CCR0) sets a software reset, interrupt signal, and configuration index. Bit 7 Read Write Initial Value Bit no. 7 Bit name SRESET 0 Bit 6 LevIREQ -- 1 Operation 0 Value 0 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Configuration index 0 0 Function When 0 is written to this bit, the MB86967 enters the hardware reset state or the same state as that after hardware reset. Reset state; this is the same as the hardware reset state except that this bit is not cleared. When this bit is set, the pointers and registers in the LAN controller are also reset. Since the MB86967 is in the level interrupt request mode, 1 is always read in the I/O interface card mode. This bit is not affected by writing. These bits are used to select 32 configuration indexes provided for the card. 0 0
SRESET Read/Write (Software Reset)
1
6
LevIREQ (Level Interrupt Request) CONF INDX (Configuration Index)
Read
--
5 to 0
Read/Write
--
66
MB86967
(2) CCR1: Card Configuration Status Register (00007F2H) This register indicates the configuration status of the card. Bit 7 Read Write Initial Value Bit no. 7 Bit name Changed (State Change) Changed -- 0 Bit 6 0 -- 0 Operation Read Bit 5 IOis8 0 Value -- Bit 4 0 -- 0 Bit 3 0 -- 0 Bit 2 PwrDwn 0 Function This bit is 1, indicating that the bit value (bit 5) of the pin replacement register is 1. The value of bit 5 of the pin replacement register, indicating that this bit becomes 0. This is a read-only bit and it is not affected by writing. The read value of this bit is always 0 and this bit is not affected by writing. The MB86967 enters the word transfer mode (PD0 to PD15). In this case, bit 5 (SB/SW) of the control register (DLCR6) in the LAN controller is set to 0. The MB86967 enters the byte transfer mode (PD0 to PD7). In this case, SB/-SW (bit 5) of DLCR6 in the LAN controller is set to 1. The system must set CE2 Non-active. The read value is always 0. These bits are not affected by writing. This bit clears the power-down mode. When this bit is cleared, bit 5 (STBY) of DLCR7 in the LAN controller is also cleared to 1. The power-down mode is set. When this bit is set, bit 5 (STBY) of DLCR7 is set to 0, making it possible to place the LAN controller and 10BASE-T transceiver in the standby state. Presetting bit 4 of BMPR14 in the LAN controller causes the MB86967 to enter the shutdown mode (oscillation stopped). This bit should be set after initializing the LAN controller. Return from the shutdown mode should be made by reset. See 4. Operation Sequence in PC Card Mode. The read values of these bits is always 0. These bits are not affected by writing. Bit 1 0 -- 0 Bit 0 0 -- 0
6 5
Not used IOIS8 (8-bit I/O)
Read Read/Write
-- 0
1
4 and 3 Not used 2 PwrDwn
Read Read/Write
-- 0
1
1 and 0 Not used
Read
--
67
MB86967
(3) CCR2: Pin Replacement Register (00007F4H) This register indicates the card ready or busy state. Bit 7 Read Write Initial Value Bit no. Bit name 0 -- 0 Bit 6 0 -- 0 Operation Read Read/Write Bit 5 CRdy/Bsy 0 Value -- 0 Bit 4 0 -- 0 Bit 3 1 -- 1 Bit 2 1 -- 1 Function The read values of these bits is always 0. These bits are not affected by writing. Indicates that Ready/Busy bit (bit 1) not changed (from 1 to 0 or from 0 to 1) 0 can be written to this bit only when this bit is 1 with bit 1 set to 1. Indicates that Ready/Busy changed (from 1 to 0 or from 0 to 1) 0 can be written to this bit only when this bit is 1 with bit 1 set to 1. The read value of this bit is always 0. This bit is not affected by writing. The read values of these bits is always 1. These bits are not affected by writing. Indicates card in busy state Indicates card in ready state In the IC memory card interface mode, such as power-on and reset a High level is output (when a write operation to the CCR is not performed). The read value of this bit is always 0. This bit is not affected by writing. Bit 1 RRdy/Bsy 0 Bit 0 0 -- 0
7 and 6 Not used 5 CRdy/Bsy (Ready/Busy State Change)
1
4
Not used
Read Read Read/Write
-- -- 0 1
3 and 2 Not used 1 RRdy/Bsy (Ready/Busy)
0
Not used
Read
--
(4) CCR3: Socket/Copy Register (00007F6H) Bit 7 Read Write Initial Value Bit no. 0 to 7 Bit name Not used 0 -- 0 Bit 6 0 -- 0 Operation Read Bit 5 0 -- 0 Value -- Bit 4 0 -- 0 Bit 3 0 -- 0 Bit 2 0 -- 0 Function The read values of these bits is always 0. These bits are not affected by writing. Bit 1 0 -- 0 Bit 0 0 -- 0
68
MB86967
7. I/O Address Space
I/O address space has control registers in the LAN controller and the LAN card control register; in some cases, it has ID numbers. The MB86967 supports both the independent I/O addressing mode, and overlapping I/O addressing mode. Index 0 of the 32 I/O indexes is used to address the independent I/O, and index 31 is used to address the overlapping I/O. One index has 32 bytes of address space. In the independent I/O addressing mode, the I/O address pins A4 to A0 are used. When using the overlapping I/O addressing mode in the ISA and EISA buses, I/O address space is allocated to any one of the 31 indexes. The system can select any I/O base address by writing different indexes to bits 0 to 5 of the card configuration option register. In this mode, all I/O address pins A0 to A10 are used. If 32 bytes of I/O address space are allocated to the control registers in the LAN controller, the LAN card control register, and ID numbers are as follows: Base Address +0 to F +10 +12, 14, 16, 18, 1A, 1C, 1E +11, 13, 15, 17, 19, 1B, 1D, 1F LAN card control register For setting ID numbers (only read value valid) A read value that is not used as the ID number is undefined. Reserved (The read value is undefined and writing is invalid.) Register Control registers in LAN controller
The configuration indexes and I/O base addresses to be assigned are as follows: Index CCR 7F0H Bit 0 to 5 000000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 I/O Address Space I/O function in non-active Independent I/O addressing 020H to 03FH 040H to 05FH 060H to 07FH 080H to 09FH 0A0H to 0BFH 0C0H to 0DFH 0E0H to 0FFH 100H to 11FH 120H to 13FH 140H to 15FH 160H to 17FH 180H to 19FH 1A0H to 1BFH 1C0H to 1DFH 1E0H to 1FFH Index 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 CCR 7F0H Bit 0 to 5 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 I/O Address Space 200H to 21FH 220H to 23FH 240H to 25FH 260H to 27FH 280H to 29FH 2A0H to 2BFH 2C0H to 2DFH 2E0H to 2FFH 300H to 31FH 320H to 33FH 340H to 35FH 360H to 37FH 380H to 39FH 3A0H to 3BFH 3B0H to 3DFH 3E0H to 3FFH
69
MB86967
(1) I/O-read (+0 to +10) Mode Byte access (8 bits) Word access (16 bits) High byte only REG CE2 CE1 IORD OE IOWR PA0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 1 1 1 1 0 1 0 x PD8 to PD15 Invalid Invalid Odd byte Even byte PD0 to PD7 Even byte Odd byte Even byte Invalid ROMS ROMRD ROMAD H H H H H H H H L L L L
(2) I/O-read (+12, +14, +16, +18, 1A, 1C, 1E: ID number) Mode Byte access (8 bits) Word access (16 bits) REG CE2 CE1 IORD OE IOWR PA0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 PD8 to PD15 Invalid Odd byte PD0 to PD7 Even byte Even byte ROMS ROMRD ROMAD L L L L H H
(3) I/O-write (+0 to +10) Mode Byte access (8 bits) Word access (16 bits) High byte only REG CE2 CE1 IORD IOWR WE PA0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 1 0 x PD8 to PD15 Don't care Odd byte PD0 to PD7 Odd byte Even byte ROMS ROMRD ROMAD H H H H H H H H L L L L
Don't care Even byte
Even byte Don't care
(4) I/O-write (+12, +14, +16, +18, 1A, 1C, 1E: ID number) Mode Byte access (8 bits) Word access (16 bits) REG CE2 CE1 IORD IOWR* 0 0 1 0 0 0 1 1 0 0
WE*
PA0 0 0
PD8 to PD15
PD0 to PD7
ROMS ROMRD ROMAD L L H H H H
0 0
Don't care Even byte Odd byte Even byte
* : To write the ID number, both the IOWR and WE pins must be set Active.
70
MB86967
(5) CARDCR: LAN Card Control Register (Base address +10) This is an external ROM control register that can be accessed only in the PC card mode. Bit 7 Read Write Initial Value Bit no. 7 CIS WR ENA 0 Bit 6 COMMON WR ENA 0 Bit 5 ID NUMBER WR ENA 0 Bit 4 0 -- 0 Bit 3 0 -- 0 Bit 2 0 -- 0 Bit 1 0 -- 0 Bit 0 0 -- 0
Bit name CIS WRITE ENABLE (CIS Write Enable) COMMON WR ENABLE (Common Memory Write Enable) ID NUMBER WR ENABLE (ID Number Write Enable) Not used
Operation Read/Write
Value 0 1
Function The system cannot write data to CIS in E2PROM or flash ROM. The system can write data to CIS in E2PROM or flash ROM. The system cannot write data to common memory in E2PROM or flash ROM. The system can write data to common memory in E2PROM or flash ROM. The system cannot write data to I/O space (for ID number) in E2PROM or flash ROM. The system can write data to I/O space (for ID number) in E2PROM or flash ROM. The read values of these bits are always 0s. These bits are not affected by writing.
6
Read/Write
0 1
5
Read/Write
0 1
0 to 4
Read
--
8. Initializing Card (Using MB86967 in PC Card)
Immediately after the card is installed in the system, the IC memory card interface (memory card) is selected. The following instructions describe how to switch to the I/O card interface: a. The system reads card attribute data (CIS) for setting operating environments. b. The data is written to the card configuration register (CCR). At this time, the LAN controller is set to the 8-bit interface or 16-bit interface by setting the bit 5 (IOIS8) of CCR1. c. The Ethernet ID numbers read from CIS or I/O space are written. Note: Switch from the I/O card interface to IC memory card interface by setting the external RESET pin or the SRESET bit of CCR0.
71
MB86967
s RESET, STANDBY, AND SHUTDOWN MODES
1. PC Card Mode
Interface Input of 1 to external reset register LAN Controller Operation * The CCR is initialized. * The I/O card interface is switched to the IC memory interface. * The LAN controller and 10BASE-T transceiver are also initialized. Same as above, except this bit not cleared * The CCR is initialized. * The I/O card interface is switched to the IC memory interface. * The LAN controller and 10BASE-T transceiver are also initialized. DLCR6 Bit 7 ENA DLC = 1 * The LAN controller is initialized. The previous values of the control registers (DLCR, MAR, and BMPR) in the LAN controller are retained. * The TP or AUI transceiver is in the power-down mode.
CCR0 Bit 7 SRESET = 1
CCR1 Bit 2 PwrDwn = 1
DLCR7 Bit 5 BMPR14 Bit 4 * Standby mode STBY = 0* SHUT DWN MODE = 0 The clock stops and current consumption is reduced to about 10%. BMPR14 Bit 4 * Shutdown mode SHUT DWN MODE = 1 Crystal oscillation stops and current consumption is reduced to about 1%.
* : The STBY bit of the DLCR7 is set automatically.
2. ISA Bus Mode
Operation Input of 1 to external reset register Write to reset registers: RES0 to RES7 (any values) DLCR6 Bit 7 ENA DLC = 1 * The LAN controller and 10BASE-T transceiver are initialized. * The LAN controller and 10BASE-T transceiver are initialized but BMPR16 and BMPR17 are not. * The LAN controller is initialized. The previous values of the control registers (DLCR, MAR, and BMPR) in the LAN controller are retained. * The TP transceiver is in the power-down mode. BMPR14 Bit 4 SHUT DWN MODE = 0 BMPR14 Bit 4 SHUT DWN MODE = 1 * Standby mode The clock stops and current consumption is reduced to about 10%. * Shutdown mode Crystal oscillation stops and current consumption is reduced to about 1%.
DLCR7 Bit 5 STBY = 0
72
MB86967
3. General-purpose Bus Mode
Operation Input of 1 to external reset register DLCR6 Bit 7 ENA DLC = 1 * The LAN controller and 10BASE-T transceiver are initialized. * The LAN controller is initialized. The previous values of the control registers (DLCR, MAR, and BMPR) in the LAN controller are retained. * The TP transceiver is in the power-down mode. BMPR14 Bit 4 SHUT DWN MODE = 0 BMPR14 Bit 4 SHUT DWN MODE = 1 * Standby mode The clock stops and current consumption is reduced to about 10%. * Shutdown mode Crystal oscillation stops and current consumption is reduced to about 1%.
DLCR7 Bit 5 STBY = 0
73
MB86967
4. Operation Sequence in PC Card Mode
Operable state
Power on
CCR0: SRESET = High
RESET pin = High
Is crystal oscillation stabilized? YES Write 1 to ENA DLC bit of DLCR6. CCR0: SRESET = Low
NO
Is crystal oscillation stabilized? YES RESET pin = Low
NO
Switch from IC memory card interface to I/O card interface.
Controller is in initialized state. *2 Write 1 to PwrDwn bit of CCR1. Set DLCR, MAR, and BMPR registers.
BMPR14 Bit 4 = 0? YES
NO
*1
200 s WAIT?
NO
Standby state
Shutdown state
Write 0 to ENA DLC bit of DLCR6.
*3 Write 0 to PwrDwn bit of CCR1.
*1: The time for setting the DLCR, MAR, and BMPR registers may be included in the waiting time of 200 s. *2: The STBY bit of DLCR7 is automatically set to 0. *3: The STBY bit of DLCR7 is automatically set to 1. In the PC card mode, the STBY bit of DLCR7 is set from the PwrDwn bit of CCR1 to as shown in *2 and *3. Direct change (from 0 to 1 or from 1 to 0) is not allowed. * Standby state: The clock to each circuit stops but crystal oscillation does not. * Shutdown state: Crystal oscillation stops.
74
MB86967
5. Operation Sequence in ISA Bus Mode
Operable state
Power on
Write to reset register.
RESET pin = High
RESET pin = High
200 ns WAIT? YES
NO
200 ns WAIT? YES
NO
Is crystal oscillation YES RESET pin = Low
NO
Write 1 to ENA DLC bit of DLCR6. Mode? Jamperless
Jamper
50 ms WAIT? YES
NO
Initialized state
Write 0 to STBY bit of DLCR7.
Set DLCR, MAR, and BMPR registers.
BMPR14 Bit 4 = 0? YES
NO
*
200 s WAIT? YES Write 0 to ENA DLC bit of DLCR6.
NO
Standby state
Shutdown stat
Write 1 to STBY bit of DLCR7.
* : The time for setting the DLCR, MAR, and BMPR registers may be included in the waiting time of 200 s. * Standby state: The clock to each circuit stops but crystal oscillation does not. * Shutdown state: Crystal oscillation stops. 75
MB86967
6. Operation Sequence in General-purpose Bus Mode
Operable state
Power on
RESET pin = High
RESET pin = High
200 ns WAIT? Write 1 to ENA DLC bit of DLCR6. YES
NO
Is crystal oscillation stabilized? YES RESET pin = Low
NO
Initialized state
Write 0 to STBY bit of CCR1.
Set DLCR, MAR, and BMPR registers.
BMPR14 Bit 4 = 0? YES
NO
*
200 s WAIT? YES Write 0 to ENA DLC bit of DLCR6.
NO
Standby state
Shutdown state
Write 1 to STBY bit of DLCR7.
* : The time for setting the DLCR, MAR, and BMPR registers may be included in the waiting time of 200 s. * Standby state: The clock to each circuit stops but crystal oscillation does not. * Shutdown state: Crystal oscillation stops.
76
MB86967
s SOFTWARE SUPPORT FOR POPULAR NETWORK OPERATING SYSTEMS
1. LAN Node Drivers
The so-called driver is the hardware-dependent portion of the software complement for a network node. It's purpose is to marry a specific hardware configuration to a more-or-less generic interface provided by the networking software. Network software suppliers provide such generic interfaces for drivers to encourage universal support from a variety of hardware products. By partitioning or layering the software into a stack of components with standardized interfaces between the layers, the job of integrating various hardware and software offerings with a particular network operating system becomes easier. More drivers will become available, and everyone benefits. As seen in Figure 9, which depicts a model of LAN node components, the driver sits between the generic network software and the hardware, and acts as a bridge between the system and the node hardware. The interface of the driver to the network software and its applications is a generic interface and virtually the same for all drivers running on a given operating system. But the driver comprehends the configuration and nuances of the hardware, and optimizes it's performance in the system. A good, well-written driver is a positive advantage to the system, allowing it to achieve its performance potential; whereas a poor driver will limit the performance and reliability of the system. The best drivers have a certain intimacy with the hardware, which allows them to take full advantage of its features. High data throughput, data integrity, and reliable operation are the key goals for which every nodedriver writer should strive. In addition, the final driver should be efficient, by requiring minimum host execution time. These are all things the end user will and should take for granted; if they are not supplied with the design, there will be no customer satisfaction. Most network software suppliers offer technical support for third-party driver development. This often comes in the form of a developer's kit that includes a manual and software examples. Some suppliers also offer test suites and certification testing to verify the driver product, because they know that good drivers benefit both users and suppliers.
IN Q Network Software OUT Q
Network
MB86967
Driver
Figure 9 Model of LAN Node
77
MB86967
2. What's in a Driver?
Typical node drivers manage the movement of packet data between system memory and the network, and vice versa, as well as providing diagnostic testing, error processing, and error statistics on-demand for the system. The first thing a driver does when the system is powered up is system check-out, which may include buffer memory testing, and loopback testing of the transmit and receive circuits. If the network supports it, as does Ethernet, for example, the testing may include sending and receiving test packets on the network to verify the ability to communicate. As shown in Figure 10, the driver provides control of the initialization, interrupt and branch control processes, supporting both the transmit and the receive functions.
Start
Interrupt Branch Control
Newtwork Software Transmit Request
Initialization
Interrupt Service Request
Receive Read
Transmit Write
Exit
Exit
Exit
Figure 10 Software Driver Model
Figure 11 shows an example in flow chart form of a check-out routine written for the Fujitsu MB86967 Controller. The driver first initializes the control and status registers in the controller for memory and loopback testing. Loopback and memory testing are conducted simultaneously by transmitting memory test patterns from the transmit buffer area of memory to the receive buffer area using loopback. This test sequence simultaneously exercises and tests the transmitter, the receiver and the buffer memory. The loopback/memory startup test is performed by first loading a test pattern in the form of several packets into the controller chip's transmit buffer, then transmitting the packets in loopback mode. The loopback transmission path through the chip exercises the data link controller as well as the encoder and decoder circuitry, but does not affect the network. The MB86967 controller has a unique buffer memory architecture which pipelines packets through the system in both directions, optimizing data through-put. MB86967's buffer controller provides all the pointer management for accessing the buffer automatically, greatly reducing the complexity of the driver and minimizing the software overhead. Receive packets with errors are automatically purged by MB86967. When a collision occurs, MB86967 automatically re-transmits without host interaction. These features provide high data throughput while minimizing the host and memory overhead. At the successful conclusion of the tests, the driver starts up the MB86967 chip for regular service on the network.
78
SCAN FOR ETHERCOUPLER(S) EtherCoupler Found? NO Exit Call or queue disposition Report EtherCoupler not found
Start
Scan I/O Address(es) to find EtherCoupler(s) YES
Report EtherCoupler Found
INITIALIZE ETHERCOUPLER(S) SELF TEST Perform Self Tests Reprogram I/O Address(es) if necessary to resolve contention with other devices Read and interpret EEPROM settings data if available Determine type of and configure medium Self Tests Passed? Allocate interrupt request channel Install Interrupt Service Routine (ISR) Set operating modes into EtherCoupler registers Read ID EEPROM for Ethernet address Load Ethernet address into NODE ID Registers Initialize software flags and values Exit YES Configure for network operation Report ready for network operation NO
Report error(s) Call or queue disposition Exit
Figure 11 Start-up Testing
MB86967
79
MB86967
3. Operating on the Network
Driver code for operating on the network might be partitioned into three main modules as shown in the example for the MB86967 controller in this section. The modules, shown in Figures 12, 13, and 14 are Transmit Packet Write, in which packets to be transmitted are moved from host memory to the point marked TX PKT WRITE. Transmission takes place in two steps. First, packets to be transmitted are loaded into the transmit buffer. Secondly, when the transmitter is not busy, it will be started to transmit the stored packets. Each of these steps may have to wait for resources. The packets cannot be loaded unless there is buffer space available. MB86967 provides the option of a single or two independent transmit buffers. With two buffers there is usually no waiting. The transmitter cannot transmit but one buffer full of packets at a time. To manage these resources, two software flags are used, TBUF STAT and TX STAT, the status of the transmit buffer and the transmitter respectively. TBUF STAT refers to the current buffer which might be available to the driver for loading. Its status can be Busy if no buffer is available, Loading when in the process of being loaded, in Standby if ready to transmit, but not full, ready and Full or Empty. The transmitter status can be either Busy or Idle. Packet length is checked during the loading process to assure that the ISO/ANSI/IEEE 8802-3 length requirements are met. Packets ready to be loaded can be loaded into an Empty or Standby buffer, the latter being a buffer with packets waiting for the transmitter to become idle. If a standby buffer has more room for packets, additional packets can be loaded until it is full. The Empty buffer is available for loading and has no packets. The driver takes ownership of an Empty or Standby buffer by changing its status to Loading. After the packets are loaded, the transmit status flag is checked for an idle transmitter. If idle, it can be immediately started to transmit the contents of either a Full or Standby buffer. When the transmitter of the MB86967 chip is started, buffer status also changes. In single buffer mode, starting the transmitter makes the single buffer unavailable to the system. In dual buffer mode, starting the transmitter re-allocates its previously-transmitted buffer as an empty buffer, available for loading. If the transmitter is busy, the routine will suspend execution at that point pending an idle transmitter. Two key interrupts used in this example are the receive packet interrupt (RX PKT), indicating that one or more packets has been received since the interrupt was last enabled, and the transmitter done interrupt (TX DONE), indicating that the transmitter has finished transmitting the contents of its current buffer. The interrupt service routine for network operation, illustrated in Figure 13, is short and sweet. If the receive packet interrupt has occurred, it calls or queues the routine for reading packets (RX PKT READ). Further receive interrupts are masked until the driver has emptied the receive buffer. This prevents redundant interrupts which would otherwise occur if packets come in during the read sequence. If the transmitter done interrupt has occurred, the status flags are updated, and appropriate action is taken to satisfy pending activity, if any, with the newly available buffer and/or transmitter resource. The driver is structured to read all receive packets in the buffer whenever one or more packets arrive. A status bit in MB86967 (BUF EMPTY) indicates whether the receive buffer is empty or not (indicating whole packets only). The packet read routine, shown in Figure 14, starts by masking further receive interrupts until it has emptied the buffer and suspended execution. This prevents redundant interrupts which would otherwise occur if packets come in during the read sequence. As each packet is read, it can be read in parts. If after reading the first part the packet is not of interest, the rest can be discarded without being moved to host memory using MB86967's Skip Packet feature. Reading will continue until the buffer is empty, as indicated by RBUF EMPTY bit. The Transmit Packet Write Routine, shown in Figure 12, and the Receive Packet Read Routine, shown in Figure 14, together comprise the driver core, which can be called by the network software or from the Network Interrupt Service Routine, shown in Figure 13. Once called, this core routine transfers both transmit and receive packets until there are no more to be transferred, then exits or returns. If packets are transferring, this core routine avoids locking out either the transmitter or the receiver while the other is very busy, by alternating between the two after a fixed number of packets, set by TX MAX and RX MAX. While in operation, the core routine polls key status bits. Interrupts are disabled to prevent unnecessary interrupts while the core is executing. 80
TX PKT WRITE TX STARTUP From Fig. 14 B Set TX CNT = 0 Mask Interrupts NO
Set TX CNT = 0 Mask Interrupts
TX Request Pending? YES Standby TBUF STAT? Empty LOAD TX BUFFER Set TPKT CNT = 0 NO To Fig. 14 A Set TBUF FREE = TBUF SIZE Standby or Full TBUF STAT? RX PKT? YES Busy,or Empty Busy, or Full
Calculate/retrieve length of next packet Increment TX CNT
Short Packet Error <60 Length in bytes? Report error Call or queue disposition 60 or 1515 TX DONE? >1514 Long Packet Error
Report error
Call or queue disposition
NO
YES YES Will it fit in buffer? TX STAT? TBUF STAT? Idle NO TX DONE? YES START TRANSMITTER Set TX STAT to Busy Clear TX DONE Write packet count (TPKT CNT) into BMPR10<6:0>, and write 1 to TX START Set TX STAT to Idle Set TBUF STAT to Empty TX Request Pending? YES Set TBUF STAT to Empty Dual TBUF MODE? Single Set TBUF STAT to Busy NO Enable Interrupts Full, or Standby Empty, or Standby NO Busy Busy,or Empty TBUF STAT? Full or Busy TX Buffer Full Set TBUF STAT to Full Defer remainder of packets for processing later
Load length into Transmit Buffer Move packet data into Transmit Buffer Recalcuate TBUF FREE
TX STAT?
Idle
Figure 12 Transmit Packet Write Routine
To TX STARTUP Set TBUF STAT to Standby NO TX CNT = TX MAX? YES
Busy
TX DONE?
YES
NO
TX Request Pending?
NO
YES
To TX PKT WRITE
Exit
MB86967
NO
TX CNT = TX MAX?
YES
81
MB86967
A driver such as the one illustrated in this section might typically occupy 4 to 6 kilobytes on its distribution diskette. The host-resident portion, when loaded for network operation, might use typically 2 to 3 kilobytes of host memory. A set of quality software drivers bundled with the hardware is well worth providing to LAN equipment customers. By providing better performance and reliability, good drivers will enhance both customer satisfaction and sales, while reducing customer service calls. Table 6 represents typical control and status parameter used in MB86967 Network Drivers.
Network ISR
Interrupt
Read Status Registers Report, clear and process error interrupts, if any
YES RX PKT? NO
Clear and mask receive interrupts Call or queue RX PKT READ
YES TX DONE?
Clear and mask transmit interrupts Set TX STAT to Idle
Dual TX MODE? Single
Call or queue TX STARTUP
Set TBUF STAT to Empty Call or queue TX PKT WRITE
Retum from interrupt
Figure 13 Network Interrupt Service Routine
82
MB86967
RX PKT READ "A" From Flg. 12 Set RX CNT = 0 Mask interrupts
RBUF EMPTY? NO
YES
To Flg. 12 "B"
RC CNT = RX MAX? NO
YES
Read packet header from buffer Set RPKT LEFT to length given in header Increment RX CNT Clear RX PKT
Read all or part of packet Recalculate RPKT LEFT, subtracting byte count read Process packet
=0
RPKT LEFT?
>0
Read more of packet?
YES
NO
8bytes RPKT LEFT?
Read and discard balance of packet
> 8bytes
Write 04H to Skip Packet Register, BMPR14 Delay 260 ns minimum or poll BMPR14 utill it is 00H
Figure 14 Receive Packet Read Routine
83
MB86967
Table 6 Control and Status Parameters
Symbol DLC EN Type Name Description When high, resets all buffer memory pointers and disables both the transmitter and the receiver circuits. When low, enables buffer memory, transmitter and receiver. When set low, places MB86967 in internal loopback mode. When high, indicates that there is at least one complete packet stored in the receive buffer, ready to read. When low, indicates there are no packets ready to read in the receive buffer. The number of bytes remaining in the receive packet being read from the buffer. Calculated by the driver from the original length given by MB86967 in the 3rd and 4th bytes of the receive packet header, less the number of bytes already read out. A running count of the number of packets transferred from the receive buffer to system memory since entering the Receive Packet Read Routine. This parameter can share the same memory location with TX CNT, because both are not used concurrently in the same subroutine.
Register DATA LINK Bit CONTROL ENABLE Register LOOPBACK Bit CONTROL Register RECEIVE Bit BUFFER EMPTY Software RECEIVE Value PACKET LENGTH LEFT Software RECEIVE Value TRANSFER COUNT
LBC RBUF EMPTY RPKT LEFT
RX CNT
RX MAX
Software MAXIMUM The maximum number of packets that may be processed in the Value VALUE FOR RX Receive Packet Read Routine.before passing control to the Transmit CNT Packet Write Routine. This parameter can be fixed or allowed to vary according to need. Typical range for this parameter is 15 - 32. Software TRANSMIT Value BUFFER FREE SPACE The number of available bytes remaining in the transmit buffer being loaded with packets by the driver. Calculated by driver.
TBUF FREE TBUF MODE
Register TRANSMIT The configuration of the transmit buffer space, SINGLE buffer or Bits BUFFER MODE DUAL buffers. The size in bytes of each transmit buffer, which depends on initial configuration parameters for the buffer memory. Current status of the transmit buffer available for loading packets. Maintained by the driver. TBUF STAT Empty Busy Value Description Current transmit buffer available to system bus is completely empty. No buffer is currently available to the system bus because a) MB86967 is in single-buffer mode and b) the transmitter is using the buffer. The buffer currently available to the system bus has one or more packets in it, but may still have room for additional packet(s). The buffer currently available to the system bus has one or more packets in it, and does not have room for the next packet presented to the driver from the transmit queue.
TBUF SIZE Software TRANSMIT Value BUFFER SIZE TBUF STAT Software TRANSMIT Value BUFFER STATUS
Standby
Full
84
MB86967
Symbol TPKT CNT
Type
Name
Description The number of packets loaded into the current transmit buffer by the driver. Value is counted by driver. This value is written into MB86967 register BMPR10<6:0> at the time transmitter is started. A running count of the number of packets transferred from system memory to the transmit buffer since entering the Transmit Packet Write Routine. This parameter can share the same memory location with RX CNT, because both are not used concurrently in the same subroutine. When transmitter finishes transmitting, MB86967 sets this bit high. Normally cleared by driver prior to starting transmitter. Hardware reset or DLC EN being set high also clears this bit. The maximum number of packets that may be processed in the Transmit Packet Write Routine before passing control to Receive Packet Read Routine. This parameter can be fixed or allowed to vary according to need. Typical range for this parameter is 15-32. When set high, activates transmitter to transmit all packets in the current transmit buffer. See also TPKT CNT. Current status of the transmitter, maintained by driver.
Software TRANSMIT Value PACKET COUNT Software TRANSMIT Value TRANSFER COUNT
TX CNT
TX DONE
Register TRANSMITTER Bit DONE Software MAXIMUM Value VALUE FOR TX CNT Register START Bit TRANSMITTER Software TRANSMIT Value BUFFER STATUS
TX MAX
TX START TX STAT
TX STAT Busy Idle
Value Description Transmitter has not finished transmitting packets previously given to it to transmit. Transmitter has finished transmitting all packets in its buffer.
85
MB86967
s ABSOLUTE MAXIMUM RATINGS
(GND = 0 V) Parameter Power supply voltage Input voltage Output voltage Storage temperature Operating temperature Output current Symbol VDD VI VO Tstg Top IO Rating Min. VSS - 0.5 VSS - 0.5 VSS - 0.5 -55 -40 -40 Max. +6.0 VDD + 0.5 VDD + 0.5 +125 +85 +40 Unit V V V C C mA
* : Duration of voltage applied is within 1 sec per terminal. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Operating temperature TTL "H" level output current Symbol VDD Ta IOH Value Min. 4.75 0 -- -- -- -- TTL "L" level output current Crystal oscillator frequency IOL fXtal -- -- *1: Applies to P92 (IREQ, IREQ0, INT) *2: Applies to LED terminal (open-drain output) and P92 (IREQ, IREQ0, INT) *3: Applies to P3 (WAIT, IOCHRDY, READY) and P84 (IOIS16) WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Typ. 5.00 -- -2.0 -4.0* 3.2 12.0*2 24.0*
3 1
Max. 5.25 +70 -- -- -- -- -- --
Unit V C mA mA mA mA mA mA MHz
-8.0*3
20.000 0.005%
86
MB86967
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Symbol IDD Power supply current TTL "H" level output voltage TTL "L" level output voltage TTL "H" level input voltage TTL "L" level input voltage TTL input leak current TTL HI-Z leak current*
4
Conditions Operation state*1 Power down*2 Shut down*3 IOH = -2 mA, -4 mA, -8 mA IOL = 3.2 mA, 12 mA IOL = 24 mA TTL standard cell TTL schmitt trigger cell TTL standard cell TTL schmitt trigger cell VI = 0 to VDD VI = 0 V to VDD
Value Min. -- -- -- 4.0 VSS VSS 2.2 2.4 VSS VSS -10 -10 100 Typ. 70 10 0.1 -- -- -- -- -- -- -- -- -- -- Max. 100 15 0.5 VDD 0.4 0.5 VDD VDD 0.8 0.6 10 10 --
Unit mA mA mA V V V V V V V A A k
IDDP IDDS VOH VOL VIH VIL ILI ILZ RPUPD
Input pull-up/pull-down resistor
*1: For TP in operation. *2: With the use of register settings, enable power saving mode, including RESET=Low, TP input/input with pull-up resistor = OPEN, other input terminal = Low or High, All output terminals = OPEN *3: With the use of register settings, enable shut-down mode, including RESET=Low, TP input/input with pull-up resistor = OPEN, other input terminal = Low or High, All output terminals = OPEN *4: Leak current when the TTL I/O terminal is in a high-impedance state.
87
MB86967
2. TP Interface DC Characteristics
(VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter TPO "H" level output voltage TPO "L" level output voltage TPO "H" level output current TPO "L" level output current TPO output impedance TPI input impedance TPI input bias voltage TPI differential input voltage TPI differential input squelch threshold voltage TPI differential input non-squelch threshold voltage Symbol VTOH VTOL ITOH ITOL ZTO ZTI VTIBIAS VTID VTIDSH VTIDNSH Conditions ITOH = 24 mA ITOL = 24 mA -- -- -- -- -- -- -- -- Value Min. VDD - 0.5 VSS -- -- -- -- -- 0.58 -- -80 Typ. -- -- 24.0 24.0 10.0 10.0 3.3 -- -420 0 Max. VDD 0.4 -- -- -- -- -- 3.1 -- +80 Unit V V mA mA k V V mV mV
88
MB86967
3. AC Characteristics
(1) Bus Timing (PC card mode, CCR read cycle) (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Setup time for address, CE1, CE2, REG prior to OE assert Hold time for address, CE1, CE2, REG after OE negate Output delay time for read data Output hold time for read data Symbol t1 t2 t3 t4 Value Min. 5 5 -- 5 Max. -- -- 40 -- Unit ns ns ns ns
PA
t2
REG
CE1, CE2
OE
t1
PD
t3 t4
89
MB86967
(2) Bus Timing (PC card mode, CCR write cycle) (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Setup time for address, CE1, CE2, REG prior to WE assert Hold time for address, CE1, CE2, REG after WE negate Setup time for write data input Hold time for write data input Symbol t1 t2 t3 t4 Value Min. 5 5 10 5 Max. -- -- -- -- Unit ns ns ns ns
PA
t2
REG
CE1, CE2
WE
t1
PD
t3 t4
90
MB86967
(3) Bus Timing (PC card mode, CIS read) (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Setup time for address, CE1, CE2, REG prior to OE assert Hold time for address, CE1, CE2, REG after OE negate ROMS assert output delay after OE assert ROMS negate output delay after OE negate ROMRD assert output delay after OE assert ROMRD negate output delay after OE negate Symbol t1 t2 t3 t4 t5 t6 Value Min. 5 5 -- -- -- -- Max. -- -- 30 30 30 30 Unit ns ns ns ns ns ns
PA
REG
CE1, CE2
OE
t1
t2 t3 t4
ROMS
t5 t6
ROMRD
91
MB86967
(4) Bus Timing (PC card mode, CIS write) (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Setup time for address, CE1, CE2, REG prior to WE assert Hold time for address, CE1, CE2, REG after WE negate ROMS assert output delay after WE assert ROMS negate output delay after WE negate Symbol t1 t2 t3 t4 Value Min. 5 5 -- -- Max. -- -- 30 30 Unit ns ns ns ns
PA
REG
CE1, CE2
WE
t1
t2
IOWR
t3
t4
ROMS
92
MB86967
(5) Bus Timing (PC card mode, common memory read) (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Setup time for address, CE1 prior to OE assert Hold time for address, CE1 after OE negate ROMS assert output delay after OE assert ROMS negate output delay after OE negate ROMRD assert output delay after OE assert ROMRD negate output delay after OE negate Symbol t1 t2 t3 t4 t5 t6 Value Min. 5 5 -- -- -- -- Max. -- -- 30 30 30 30 Unit ns ns ns ns ns ns
PA
CE1
OE
t1 t3 t4
t2
ROMS
t5 t6
ROMRD
93
MB86967
(6) Bus Timing (PC card mode, common memory write) (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Setup time for address, CE1 prior to WE assert Hold time for address, CE1 after WE negate ROMS assert output delay after WE assert ROMS negate output delay after WE negate Symbol t1 t2 t3 t4 Value Min. 5 5 -- -- Max. -- -- 30 30 Unit ns ns ns ns
PA
CE1
WE
t1
t2
t3
t4
ROMS
94
MB86967
(7) Bus Timing (PC card mode, I/O read cycle) (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Setup time for address, CE1, CE2, REG prior to IORD assert Hold time for address, CE1, CE2 after IORD negate Hold time for REG after IORD negate Output delay for read data after IORD assert Output hold for read data after IORD negate Read pulse width Output delay for INPACK assert after IORD assert Output delay for INPACK negate after IORD negate Output delay time of WAIT assert from IORD assert Output delay time of WAIT negate from IORD assert Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Value Min. 5 5 0 -- 10 30 -- -- 5*1 -- Max. -- -- -- 44 -- -- 45 45 35*1 175*2 Unit ns ns ns ns ns ns ns ns ns ns
*1: WAIT is asserted only when the write access conflicts with that of the network on reading the buffer memory port (BMPR8). *2: WAIT is asserted only when the write access conflicts with that of the network on reading the buffer memory port (BMPR8). This value will be 2.15 s when the bus write error occurs on reading the buffer memory port.
PA
t2
REG
t3
CE1, CE2
t6
IORD
t1 t7 t8
INPACK
t9
WAIT
t10
PD
t4 t5
95
MB86967
(8) Bus Timing (PC card mode, I/O write cycle) (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Setup time for address, CE1, CE2, REG prior to IOWR assert Hold time for address, CE1, CE2 after IOWR negate Hold time for REG after IOWR negate Setup time for write data input Hold time for write data input Write pulse width Output delay time for IOIS16 assert from address Output delay time for IOIS16 negate from address Output delay time for WAIT assert from IOWR assert Output delay time for WAIT negate from IOWR assert Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Value Min. 5 5 0 10 5 36 -- -- 5*1 -- Max. -- -- -- -- -- -- 35 35 35*1 175*2 Unit ns ns ns ns ns ns ns ns ns ns
*1: WAIT is asserted only when the write access conflicts with that of the network on writing the buffer memory port (BMPR8). *2: WAIT is asserted only when the write access conflicts with that of the network on writing the buffer memory port (BMPR8). This value will be 2.15 s when the bus write error occurs on writing the buffer memory port.
PA
t2
REG
t3
CE1, CE2
t6
IOWR
t1 t8
IOIS16
t7 t9
WAIT
t10
PD
t4 t5
96
MB86967
(9) Bus Timing (PC card mode, ID number read from EEPROM: I/O access) (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Setup time for address, CE1, CE2, REG prior to IORD assert Hold time for address, CE1, CE2 after IORD negate Hold time for REG after IORD negate Output delay for INPACK assert after IORD assert Output delay for INPACK negate after IORD negate Output delay for ROMS assert after IORD assert Output delay for ROMS negate after IORD negate Output delay for ROMRD assert after IORD assert Output delay for ROMRD negate after IORD negate Output delay for ROMAD assert after IORD assert Output delay for ROMAD negate after IORD negate Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Value Min. 5 5 0 -- -- -- -- -- -- -- -- Max. -- -- -- 45 45 35 35 30 30 30 30 Unit ns ns ns ns ns ns ns ns ns ns ns
PA
t2
REG
t3
CE1, CE2
IORD
t1
IOWR
t4 t5
INPACK
t6 t7
ROMS
t8 t9
ROMRD
t11 t10
ROMAD
97
MB86967
(10)Bus Timing (PC card mode, ID number write from EEPROM: I/O access) (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Setup time for address, CE1, CE2, REG prior to IOWR assert Hold time for address, CE1, CE2 after IOWR negate Hold time for REG after IOWR negate Output delay for ROMS assert after IOWR assert Output delay for ROMS negate after IOWR negate Output delay for ROMAD assert after IOWR assert Output delay for ROMAD negate after IOWR negate Symbol t1 t2 t3 t4 t5 t6 t7 Value Min. 5 5 0 -- -- -- -- Max. -- -- -- 35 35 30 30 Unit ns ns ns ns ns ns ns
PA
t2
REG
t3
CE1, CE2
IOWR, WE
t1 t4 t5
ROMS
t6 t7
ROMAD
98
MB86967
(11)ISA Bus Mode Read Cycle (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter From the rising edge of SA19 to SA14, SA9 to SA0, and ALE or establishment of AEN or SBHE until IOR assert Hold time of SA19 to SA14, SA9 to SA0, AEN, SBHE from IOR negate IOR pulse width From IOR negate to IOCHRDY negate IOCHRDY pulse width (on conflict at the time of BMPR8 access) From IOCHRDY assert to SD15 to 0 enabled From IOCHRDY assert to IOR hold time From IOR assert to SD15 to 0 enabled (no conflict on bus access) From IOR negate to SD15 to SD0 high impedance From SA19 to SA14, SA9 to SA0, ALE rising edge, AEN or SBHE rising edge up to IOCS16 assert From SA19 to SA14, SA9 to SA0, ALE rising edge, AEN or SBHE rising edge up to IOCS16 negate From IOR assert to ENHB, or ENLB assert From IOR negate to ENHB or ENLB negate ALE pulse width Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Min. 15 21 50 -- -- -- 20 -- -- -- -- -- -- 30 Value Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- 20 175 30 -- 38 38 28 71 46 24 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ALE SA19 to 14, 9 to 0 AEN, SBHE IOR
t14
t3 t1 t4 t5 t7 t2
IOCHRDY
t6
SD15 to 0
t10 t8 t9 t11
IOCS16
t12 t13
ENHB, ENLB
99
MB86967
(12)ISA Bus Mode Write Cycle (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter From the rising edge of SA19 to SA14, SA9 to SA0, and ALE or establishment of AEN or SBHE until IOW assert Hold time of SA19 to SA14, SA9 to SA0, AEN, SBHE from IOW negate IOW pulse width From IOW negate to IOCHRDY negate IOCHRDY pulse width (on conflict at the time of BMPR8 access) From IOCHRDY assert to IOW hold time IOW to SD15 to 0 setup time IOW to SD15 to SD0 hold time From SA19 to SA14, SA9 to SA0, ALE rising edge, AEN or SBHE rising edge up to IOCS16 assert From SA19 to SA14, SA9 to SA0, ALE rising edge, AEN or SBHE rising edge up to IOCS16 negate From IOW assert to ENHB, or ENLB assert From IOW negate to ENHB or ENLB negate ALE pulse width Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Value Min. 15 21 50 -- -- 20 5 33 -- -- -- -- 30 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- 20 175 -- -- -- 38 71 46 24 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
ALE SA19 to 14, 9 to 0 AEN, SBHE IOW
t13
t3 t1 t4 t5 t6 t2
IOCHRDY
SD15 to 0
t9 t7 t8 t10
IOCS16
t11 t12
ENHB, ENLB
100
MB86967
(13)General-purpose Bus Mode Read Cycle (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Address setup time (from IOR assert) Address hold time (from IOR negate) IOR pulse width Output delay time for READY negate Output delay time for READY assert Output delay time for READY assert Output delay time for READY negate Output delay time for read data (from IOR assert) Output delay time for read data (from READY assert) Output delay time for read data (from READY assert) Output hold time for read data Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Value Min. 3 3 30 7*
2
Typ. -- -- -- -- -- -- -- -- -- -- --
Max. -- -- -- 26*
2 1
Unit ns ns ns ns ns ns ns ns ns ns ns
-- -- -- -- -- -- 10
175* 28 44 8 18 80
28/175*3
*1: READY is negated only when the read access is conflicted with that of the network on reading the buffer memory port (BMR8). This value would be 2.15 s when the bus read error occurs on reading the buffer memory port. *2: READY is negated only when the read access is conflicted with that of the network on reading the buffer memory port (BMR8). *3: Max time is 28 ns for normal read. Max time is 175 ns only when the read access is conflicted with that of the network on reading the buffer memory port (BMR8). This value would be 2.15 s when the bus read error occurs on reading the buffer memory port.
101
MB86967
SA3 to 0 SBHE
ECS
t1 t3 t2
IOR
t5
IOCHRDY (READY)*
t4 t7
IOCHRDY (READY)*
t6 t10 t11
SD15 to 0
t9 t8
* : The IOCHRDY output terminal allows the RDYPNSEL terminal to toggle between READY (active high) and READY (active low).
102
MB86967
(14)General-purpose Bus Mode Write Cycle (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Address setup time (from IOW assert) Address hold time (from IOW negate) IOW pulse width Delay time for READY negate output Delay time for READY assert output Delay time for READY assert output Delay time for READY negate output Setup time for write data input Hold time for write data input Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 Value Min. 3 3 36 7*
2
Typ. -- -- -- -- -- -- -- -- --
Max. -- -- -- 26*
2 1
Unit ns ns ns ns ns ns ns ns ns
-- -- -- 5 6
175* 28 -- --
28/175*3
*1: READY is negated only when the write access is conflicted with that of the network on writing the buffer memory port (BMR8). This value would be 2.15 s when the bus write error occurs on writing the buffer memory port. *2: READY is negated only when the write access is conflicted with that of the network on writing the buffer memory port (BMR8). *3: Max time is 28 ns for normal write. Max time is 175 ns only when the write access is conflicted with that of the network on writing the buffer memory port (BMR8). This value would be 2.15 s when the bus write error occurs on writing the buffer memory port.
SA3 to 0 BHE
ECS
t1 t3 t2
IOW
t5
IOCHRDY* (READY)
t4 t7
IOCHRDY* (READY)
t6 t8 t9
SD15 to 0
* : The IOCHRDY output terminal allows the RDYPNSEL terminal to toggle between READY (active high) and READY (active low).
103
MB86967
(15)General-purpose Bus Mode Write Input Inhibit Period (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Input inhibit period for IOR and IOW. Symbol t1 Value Min. 50 Typ. -- Max. -- Unit ns
IOR
IOW
t1 t1 t1
104
MB86967
(16)Single DMA Access Timing (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Delay time for DREQ negate output (from DMACK assert) Delay time for DREQ assert output (from DMACK negate) EOP pulse width Delay time for EOP assert input Setup time for EOP negate Setup time for DMACK Hold time for DMACK input Symbol t1 t2 t3 t4 t5 t6 t7 Value Min. -- -- 10 3 3 0 3 Typ. -- -- -- -- -- -- -- Max. 21 19 -- -- -- -- -- Unit ns ns ns ns ns ns ns
DREQ
t1 t2
DMACK
t6
t7
IOR, IOW
t4 t3 t5
EOP* EOP*
* : EOP input allows the values of EOP/EOP register values for bit 1 of DLCR7 to toggle between EOP (active high) and EOP (active low). Note: IOCHRDY signal timing is identical as that of bus timing.
105
MB86967
(17)Burst DMA Access Timing (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Hold time for DREQ output Hold time for DMACK input (from IOR, IOW negate) Hold time for DREQ output Hold time for DMACK input (from EOP/EOP negate) Setup time for DMACK input Symbol t1 t2 t3 t4 t5 Value Min. -- 3 4 3 0 Typ. -- -- -- -- -- Max. 32 -- 28 -- -- Unit ns ns ns ns ns
* Burst DMA access timing (Exiting DMA from the MB86967)
DREQ
*1 *2
DMACK
t1 t1 t2
IOR, IOW
*1: This transition goes low at a single cycle before the last DMA when DLCR4 bit 2 is 1. *2: This transition goes low at the last cycle of DMA when DLCR4 bit 2 is 0.
* Burst DMA access timing (When DMA is interrupted by DMACK input)
DREQ
DMACK
t5 t2 t1 t2
IOR, IOW
IOCHRDY*1
*2
*1: IOCHRDY signal timing is identical as that of bus timing. *2: Interrupt period for DMA transfer
106
MB86967
* Burst DMA access timing (When DMA is exited with the EOP input)
DREQ
t3
DMACK
t2
IOR, IOW
t4
EOP* EOP*
* : EOP input allows the values of EOP/EOP register values for bit 1 of DLCR7 to toggle between EOP (active high) and EOP (active low). Note: IOCHRDY signal timing is identical as that of bus timing.
107
MB86967
(18)Buffer Memory Read Timing * 100 ns cycle access (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Read cycle time (100 ns cycle mode) Address access time Address setup time (from BCS Low) Address hold time (from BCS High) Setup time for BOE output (from BCS High) Access time for chip select Access time for output enable Setup time for data Hold time for data Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 Value Min. -- -- 0 0 -- -- -- 15 0 Typ. 100 -- -- -- -- -- -- -- -- Max. -- 81 8 -- 5 81 49 -- -- Unit ns ns ns ns ns ns ns ns ns
t1
BA14 to 0
t3 t4
BCS
t2
BWE
t6 t7
t5
BOE
t8 t9
BD7 to 0 (Input)
108
MB86967
* 150 ns cycle access (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Read cycle time (150 ns cycle mode) Address access time Address setup time (from BCS Low) Address hold time (from BCS High) Setup time for BOE output (from BCS High) Access time for chip select Access time for output enable Setup time for data Hold time for data Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 Value Min. -- -- 0 0 -- -- -- 15 0 Typ. 150 -- -- -- -- -- -- -- -- Max. -- 81 8 -- 5 81 49 -- -- Unit ns ns ns ns ns ns ns ns ns
t1
BA14 to 0
t3 t4
BCS
t2
BWE
t6 t7
t5
BOE
t8 t9
BD7 to 0 (Input)
109
MB86967
(19)Buffer Memory Write Timing * 100 ns cycle access (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Write cycle time (100 ns cycle mode) Setup time for data Hold time for data Address hold time (from WE High) WE pulse width Address setup time (from BCS Low) Address hold time (from BCS High) Delay time for WE output (from BCS Low) Setup time for WE output (from BCS High) Address determination time Chip select determination time Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Value Min. -- 40 10 12 60 2 0 0 0 71 62 Typ. 100 -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- 8 -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns
t1
BA14 to 0
t6 t7
BCS
t10 t4 t11 t8 t5 t9
BOE
BWE
t2 t3
BD7 to 0 (Output)
110
MB86967
* 150 ns cycle access (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Write cycle time (150 ns cycle mode) Setup time for data Hold time for data Address hold time (from WE High) WE pulse width Address setup time (from BCS Low) Address hold time (from BCS High) Delay time for WE output (from BCS Low) Setup time for WE output (from BCS High) Address determination time Chip select determination time Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Value Min. -- 40 10 12 100 2 0 0 0 110 100 Typ. 150 -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- 8 -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns
t1
BA14 to 0
t6 t7
BCS
t10 t4 t11 t8 t5 t9
BOE
BWE
t2 t3
BD7 to 0 (Output)
111
MB86967
(20)Reset Timing (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Reset pulse width Register access enable start time Start time for transmit & receive operation Symbol t1 t2 t3 Value Min. 200 300 200 Typ. -- -- -- Max. -- -- -- Unit ns ns s
CHRESET
t1 t2
(-ENA DLC clear)
IOR or IOW
t3
(21)Skip Packet Timing (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Skip end time Symbol t1 Value Min. 300 Typ. -- Max. -- Unit ns
IOW
t1
IOR
(SKIP RX PKT bit set) (Next receive packet read)
112
MB86967
(22)Interrupt Output Timing (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Delay time for interrupt output clear Symbol t1 Value Min. 5 Typ. -- Max. 40 Unit ns
IOW
t1
IRQX
(23)Jabber Timing (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Max transmit time Jabber stop timer Symbol -- -- Condition -- -- Value Min. 64 480 Typ. 96 512 Max. 128 544 Unit ns ns
113
MB86967
(24)Link Test Timing (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Link pulse width for TPOPA Link pulse width for TPOPB and TPONB Link pulse transmit interval Effective link pulse receive interval Symbol t1 t2 t3 t4 Value Min. -- -- 15 4.0 Typ. 100 50 16 -- Max. -- -- 17 65 Unit ns ns ms ms
TPOPA
t1
TPOPB
t2
TPONB
t2
TPONA
TP (after predistortion)
t3
TPIP/N
t4
114
MB86967
(25)Timing for reading the EEPROM default setting information (jumperless ISA mode) (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Shift clock "H" pulse width Shift clock "L" pulse width Chip select setup time Chip select hold time DI data setup time DI data hold time DO data setup time DO data hold time Symbol t1 t2 t3 t4 t5 t6 t7 t8 Value Min. -- -- -- -- -- -- 100 100 Typ. 600 600 400 200 200 200 -- -- Max. -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns
EEPCS
t3
t1
t2
t4
EEPSK
t5 t6
EEPDI (output)
t7 t8
EEPDO (input)
EEPCS
EEPSK
EEPDI
1
1
0
A5
A4
A3
A2 A1
A0
EEPDO
0
D15 D14 D13 D12 D11 D10 D9 D8
Notes:* Use the NMC93C06 or NMC93C46 for EEPROM by National Semiconductor or its equivalent. * Control signal or data for EEPROM requires control through software when writing data or reading the node ID data. It is to be controlled so that it meets the AC timing requirements for EEPROM.
115
MB86967
(26)SQE Test Timing (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter SQE test wait timer SQE test timer (27)LED Turn-on Time (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Receive LED turn-on time Transmit LED turn-on time Collision turn-on time (28)Loopback Test (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Setup time for loopback signal (DLCR4, bit 1) prior to starting to transmit Hold time for loopback signal (DLCR4, bit1) after transmit. Symbol -- -- Value Min. 100 100 Typ. -- -- Max. -- -- Unit ns ns Symbol -- -- -- Value Min. -- -- -- Typ. 128 128 128 Max. -- -- -- Unit ms ms ms Symbol -- -- Value Min. 800 800 Typ. 1000 1000 Max. 1200 1200 Unit ns ns
116
MB86967
(29)Timing for transmitting TP (VDD = +5 V 5%, GND = 0 V, Ta = 0C to +70C) Parameter Data width for transmitting TP (1, 0, 1, 0) Data with for transmitting TP (1, 1, 1, 1, or 0, 0, 0, 0, ) Data width for end of packet (the last data: "0") Data width for end of packet (the last data: "1") Delay time from TPOPA to TPOPB or from TPONA to TPONB. * When the last data is "0"
1 0
t1 t5
Symbol t1 t2 t3 t4 t5
Value Min. -- -- -- -- -- Typ. 100 50 250 300 50 Max. -- -- -- -- --
Unit ns ns ns ns ns
1
1
0
TPOPA
t2
t2
TPOPB TPONB
TPONA
1
0
1
1
0
t3
TP (after predistortion)
* When the last data is "1"
0 1 1 0 1
TPOPA TPOPB
TPONB
TPONA
0
1
1
0
1
t4
TP (after predistortion)
117
MB86967
s SYSTEM CONFIGURATION EXAMPLE
* PC card mode
PCMCIA Card slot Address Control signal Data bus (LSB) Data bus (MSB)
* CIS * Common memory (EEPROM or FLASH ROM)
Fillter
Transformer
MB86967
10BASE-T twisted-pair cable
Various (LINK, COLLISION, RECEIVE and TRANSMIT) LEDs
Data
Address 20 pF 20 pF
Buffer SRAM 20 MHz X'tal
118
MB86967
* ISA bus mode
ISA bus Address Data Bus driver* Control signal Data
*: Option
LINK LED Fillter Collision LED Transmit LED Receiver LED ID serial EEPROM Data Address 20 pF Buffer SRAM 20 MHz X'tal 20 pF MB86967 10BASE-T twisted-pair cable Transformer
119
MB86967
* General-purpose bus mode
System bus Address Control signal Bus driver interface Control signal Data Data
LINK LED Collision LED Transmit LED Receiver LED
Fillter
Transformer
MB86967
10BASE-T twisted-pair cable
Data
Address 20 pF 20 pF
Buffer SRAM 20 MHz X'tal
120
MB86967
s 10 BASE-T INTERFACE CIRCUIT
MB86967 290 TPOPB 50 TPOPA 50 TPONA 290 TPONB TPIP 1:1 50 50 Rx Filter 4 Zo = 100 0.01 F 5 3 TX Filter 1:1 RJ45
1 2
Zo = 100
To 10BASE-T Twisted-Pair Network
TPIN
6
121
MB86967
* Recommended pulse transformer Recommended transformer for the MB86967 is as follows: Model: S556-9004-09 Manufacturer: Bel Fuse Ltd. * Overview of S556-9004-09 [External view units in inches]
0.09 14
12
10 8
DATE CODE 0.084 MAX CL "DATAIL-A"
0.56
bel
S556-9004-09 PCMCIA 1 0.79 7
0.67 R 0.015 DETAIL-A 0.01 R 0.015 0.035 0.077 287 1:1 49.9 49.9 TX FILTER Z0 = 100 OHM PIN 8 PIN 9 287 1:1 RX FILTER Z0 = 100 OHM PIN 13 49.9 49.9 PIN 14
0.1 x 6
[Internal circuit]
PIN 7 PIN 6
PIN 5 PIN 4
PIN 3 PIN 2 PIN 1
122
MB86967
Model: TLA-3M103 Manufacturer Distributor: TDK Co. * Overview of TLA-3M103 [External view units in mm]
25.7 MAX. 2.54 TYP. #16
12.5 0.3 9.5 TYP.
5.95 MAX. #9
TDK * * * Part No. Lot No. #1 #8 0.25 TYP.
0.45 TYP. * * * : COUNTRY OF ORIGIN
[Internal circuit]
1
L.P.FILTER TX L.P.FILTER
1 CT : 1 CT
8
3
6 7 1 CT : 1 CT
5 16 L.P.FILTER RX 14 12 L.P.FILTER
9
11 10
N.C. pin: 2 4 13 15
0.8 TYP.
123
MB86967
Model: 851C2N-0005 Manufacturer Distributor: Toko Co. * Overview of 851C2N-0005 [External view units in inches]
1.0 0.02
0.39 PIN 1 I.D.
0.47
0.024 0.002
0.14 0.02
0.1 0.3 0.7
[Internal circuit]
1
16
XMIT
2 3
LPF
15 14
6
11
RCV
7 8
LPF
10 9
124
MB86965B
QFP160 5 V 5% Jumperless +ISA I/F Jumper+E2PROM+ISA I/F Jumper+PROM+ISA I/F General-purpose I/F TP/AUI 64 Kbytes 8/16 bits Internal PROM or Flash ROM Test for transmit, receive, collision, link Test for transmit, receive, collision, link Test for transmit, receive, collision, link 0, 1 1, 0 Test for transmit, receive, collision, link DLCR7 bit 6, 7 DLCR 0 to 15, MAR 8 to 15, *: Change name to RES0 BMPR 8, 10 to 19, (IDRB 0 to 7 to 7)* DLCR 0 to 15, MAR 8 to 15, BMPR 8, 10 to 15, CARDCR, (ID), CCR 0 to 3 Test for transmit, receive, collision, link No No Writable by selecting Flash ROM 8 bits 8 bits 32 Kbytes 32 Kbytes TP/AUI TP General-purpose bus I/F PC card I/F General-purpose bus I/F Jumperless +ISA I/F Jumper + E2PROM + ISA I/F 5 V 5% 5 V 5% SQFP100 SQFP100
MB86964-R
MB86967
Notes
Package
Supply voltage
Operation mode
Network interface
Max buffer memory size
Buffer memory bus width
ROM interface for boot program
ROM type for boot program
LED for monitoring network status
ISA bus mode
PC card mode
General-purpose Test for transmit, bus mode receive, collision, link 1, 1 DLCR 0 to 15, MAR 8 to 15, BMPR 8, 10 to 19, IDRB 0 to 7
Device ID
Internal register
ISA bus mode
s FEATURES OF MB86965B, MB86964-R, MB86967
PC card mode
General-purpose DLCR 0 to 15, MAR 8 to 15, DLCR 0 to 15, MAR 8 to 15, DLCR 0 to 15, MAR 8 to 15, bus mode BMPR 8, 10 to 15 BMPR 8, 10 to 15 BMPR 8, 10 to 15 Yes External reset or writing IDRB0 to 7 No Internal 1: 2 Yes Selectable No Yes Internal 1: 2 Yes Selectable No Yes No No Yes External reset or writing IDRB 0-7 Yes (crystal oscillation stop) External 1:1 No 100 Yes No BMPR14 bit 5, 7 BMPR15 bit 4, 5, 7 BMPR13 bit 2 BMPR12 bit 3 BMPR13 bit 6 BMPR14 bit 4 x DLCR7 bit 5 DLCR4 bit 0
Full duplex operation
Jumperless mode default setting
Shutdown mode
TP transceiver filter
Winding ratio for TP transmit pulse transformer
Remote signalling
100 /150 termination resistor
Deleting receive long packet
MB86967
Lower Squelch
125
MB86967
s ERRATA SHEET
Category Summary Power supply OFF sequence in PC card mode,. Whin the CIS area is prepared with an EEPROM device, MB86967 mulfunctions with miswriting occasionally for the CIS area (This error depends on the type of PC.)
Recommendation Please insert the OR-gate between MB86967 and EEPROM. As a result. even if Pin 95 is driven to Low, it does not influence EEPROM.
MB86967 P95 P98
EEPROM /WE /CS
PCMCIA /WE
126
MB86967
s ORDERING INFORMATION
Part number MB86967PFV Package 100-pin Plastic LQFP (FPT-100P-M05) Remarks
127
MB86967
s PACKAGE DIMENSION
100-pin Plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
75
14.000.10(.551.004)SQ
51
1.50 -0.10 +.008 .059 -.004
+0.20
(Mounting height)
76
50
12.00 (.472) REF INDEX
15.00 (.591) NOM
Details of "A" part 0.15(.006)
100
26
0.15(.006) 0.15(.006)MAX
LEAD No.
1
25
"B"
+0.05
"A" 0.50(.0197)TYP 0.18 -0.03 +.003 .007 -.001
+0.08
0.40(.016)MAX 0.127 -0.02 +.002 .005 -.001
0.08(.003)
M
Details of "B" part 0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0.500.20(.020.008) 0~10
C
1995 FUJITSU LIMITED F100007S-2C-3
Dimensions in mm (inches)
128
MB86967
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9811 (c) FUJITSU LIMITED Printed in Japan
129

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